F. J. Ferguson and J. P. Shen, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. on Computer-Aided Design, Nov. 1988, pp. 1181-1194.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....Faults . 7 Results for Test Point Insertion in Benchmark Circuits . 12 1. INTRODUCTION A common physical defect in MOS technologies is a short between two signal lines which results in a bridging fault [Shen 85] Ferguson 88] Detecting bridging faults during the test process is very important for achieving high quality levels. Bridging faults can be detected with either IDDQ testing [Levi 81] Acken 83] or conventional voltage testing. IDDQ testing involves monitoring the quiescent power supply current in CMOS ....

....G2 Output Wired and Wired or G1 Dominant G2 Dominan 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 Figure 1. Example of Gate Level Bridging Fault Models If the layout of the circuit is known, inductive fault analysis techniques can be used to identify a set of probable bridging faults [Ferguson 88] Jee 93] Circuit level models can then be used to more accurately predict the behavior of each bridging fault. Several different methods have been proposed with various tradeoffs between accuracy and simulation time [Acken 88, 91, 92] Lee 91] Hajj 92] Greenstein 92] Maxwell 93] ....

Ferguson, F.J., and J.P. Shen, "A CMOS Fault-Extractor for Inductive Fault Analysis," IEEE Transactions on Computer-Aided Design, Vol. 7, No. 11, pp. 1181-1194, Nov. 1988.

....redundant faults with respect to the patterns applied during BIST, thus the logic is fully tested during BIST. 2. 3 Test Point Insertion for Non Feedback Bridging Faults A common physical defect in MOS technologies is a short between two signal lines which results in a bridging fault [Shen 85] Ferguson 88] Although bridging faults are generally more random pattern testable than stuck at faults [Millman 89] examples are shown in [Touba 96c] to illustrate that some bridging faults are much less random pattern testable than stuck at faults. Data is presented which indicates that even after ....

Ferguson, F.J., and J.P. Shen, "A CMOS Fault-Extractor for Inductive Fault Analysis," IEEE Transactions on Computer-AidedDesign, Vol. 7, No. 11, pp. 1181-1194, Nov. 1988.

....and findings. 2 FAULTS AND TEST MODELS The conventional methods for testing CMOS circuits use a single stuck at fault model [1] However, there has been a growing amount of evidence suggesting that the single stuck at fault model is limited and cannot model all the faults in CMOS VLSI circuits [4, 5, 13]. Additional fault models such as opens, shorts, and some others should also be used to achieve high fault coverage. The IDDT testing method is based on monitoring the switching behavior of a circuit rather than just the output logic state [13] Monitoring the switching behavior provides ....

F. J. Ferguson and J. P. Shen, "CMOS fault extractor for inductive fault analysis," in IEEE Trans. on Computer-Aided Design, pp. 1181-- 1194, November 1988.

....an I DDQ test for a given BF. The criteria used to identify I DDQ tests is based on the work in [17, 20] and is different from those in our prior work [3, 4, 5, 6, 7] This will be elaborated on in section 2. Our analysis targets all BFs unlike work by others where a subset of the BFs are targeted [13, 14, 12]. This subset of BFs are extracted by analyzing the layout of the circuit based on the point defect assumption. This extraction process tries to enumerate the most likely faults. However, it suffers from some shortcoming viz, the layout is often not available; the process of fault extraction ....

F. J. Ferguson and J. P. Shen, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. on Comput.-Aided Design, Vol. 7, No. 11, pp. 1181 - 1194, 1988.

....modelling methods [11] which consider manufacturing defects in the circuit layout, were initially developed to model the yield of an IC as a function of the manufacturing process, the IC technology involved and the device itself. This approach is also referred to as Inductive Fault Analysis (IFA) [12][13] For this project, VLASIC [14] has been used as the IFA tool. Over the last few years IFA has been utilised for a number of other applications and purposes, see figure 2. For instance, IFA generated fault lists have been used for analogue fault simulation [15] Here, limitations of ....

Ferguson F J, Shen J P, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Transactions on ComputerAided Design, Vol.7, No.11, November 1988, pp 1181-94

....is more strongly driven. 2.3 Inductive Fault Analysis In order to develop P DFT techniques and to measure their improvements, it is important to know which faults can actually occur in a given layout. Inductive Fault Analysis (IFA) techniques provide a means of determining this [MFS84, Fer87, FS88] Carafe is an example of an IFA tool [JF93] Carafe is a realistic fault extractor that, given a circuit s layout, process technology information, and fabrication defect characteristics, calculates which shorts and opens can 9 occur if a spot defect modifies a circuit during the manufacturing ....

F. Joel Ferguson and John P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988. 85

....applications, CUTs usually consist of complex gates, e.g. F = AB BC AC. In this case, switch level test generation will give a correct test while gate level test generation may not guarantee the desired level of fault defect coverage. The studies pioneered by inductive fault analysis (IFA) [8] suggest that switch level defect model should be used for a high quality test generation. However, a switch level test generation program is usually much slower than a gate level test generation program [9, 10, 11, 12] In particular, from [12] we find that a switch level test generation is ....

F. J. Ferguson and J. P. Shen, "A CMOS fault extractor for inductive fault analysis," IEEE Tran. on Computer-Aided Design, pp. 1181--1194, November 1988.

....I. Introduction Obtaining low IC defect levels requires that the ICs tests have very high levels of fault coverage. Defect simulation experiments have shown that the vast majority of all local defects in MOS technologies cause changes in the circuit description that result in bridges and breaks [8, 13]. Most MOS fabrication technologies have more extra conductor defects than extra insulator defects, which makes accurate detection of bridge faults even more crucial. We use the Carafe fault extractor to extract realistic bridge faults in CMOS circuits [10] In the rest of the paper we will refer ....

F. J. Ferguson and J. P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on ComputerAided Design, 7(11):1181--1194, November 1988.

....Intuitively, dealing directly with realistic faults models at the fabrication or layout level of the circuit under test gives the best realistic defects coverage. However, the problem is that the complexity in dealing with such a low level model is tremendous. The Inductive Fault Analysis (IFA) [5] represents an important step in which the realistic defects are modeled and analyzed at the lowest fabrication level. However, test generation techniques based on IFA [1, 2] do not use such a low level fault model directly. Rather, they often map the defects found in IFA to faults in a high level ....

J. Ferguson and J. Shen, "A CMOS fault extractor for inductive fault analysis," IEEE Trans. on Computer-Aided Design, pp. 1181--1194, Nov. 1988.

....The smaller the number of Candidate Faults the more effective is the diagnosis algorithm. Fault diagnosis has been discussed in the literature, mostly for stuck at faults [1, 2, 11, 12, 19, 22, 23, 24] However, failures that occur frequently in some technologies, such as CMOS, are bridging faults [13, 14, 17]. Two approaches for diagnosing bridging faults have been studied. The first uses I ddq measurement [7, 10] and the second uses logic measurement [8, 21] In this paper we will be concerned only with logic measurement based diagnosis of bridging faults. In [21] heuristics are used to compute the ....

J. Ferguson and J. P. Shen. A CMOS fault Extractor for Inductive Fault Analysis. IEEE Trans. on Computer Aided Design, 7(11), 1988.

....report on the system s performance. 1 Introduction In the search for IC quality, bridge fault testing is becoming increasingly important. Defect simulation experiments have shown that the majority of spot defects in MOS technologies cause changes in the circuit description that result in bridges [13, 7, 11]. In order to reduce the defects per million of shipped ICs, we must determine both which defects are likely to occur and the behavior of a faulty circuit with such defects. Tests that cover 100 of the testable single stuck at faults may do a poor job of covering bridge faults [12, 6] Given this ....

F. J. Ferguson and J. P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181-- 1194, November 1988.

....faults. Bridging faults in static CMOS circuits, can be detected by monitoring the steady state current(I DDQ ) and using I DDQ Tests. This is discussed in more detail in section 2. The motivation for the studying such faults is based on recent findings that bridging faults occur very frequently [10, 11]. However, because of the large number of such faults many researchers restrict the set of bridging faults to a relatively smaller number [12] For this, the layout of the circuit is analyzed assuming the point defects. We use a different approach in that we consider all bridging faults for the ....

F. J. Ferguson and J. P. Shen, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. on Comput.-Aided Design, Vol. 7, No. 11, pp. 1181 - 1194, 1988.

....does not require explicit simulation of bridging faults. We have previously published an improvement to the technique of Millman, McCluskey, and Acken that continues to use only single stuck at information but improves on the original technique in three ways: considering only realistic bridges [12], incorporating match restriction (flagging some vectors as incapable of detecting a particular bridging fault) and incorporating match requirement (flagging some vectors as dependably detecting a particular bridging fault) Figure 1 illustrates the composite signature of a fault candidate for ....

F. J. Ferguson and J. P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988.

....an I DDQ test for a given BF. The criteria used to identify I DDQ tests is based on the work in [17, 20] and is different from those in our prior work [3, 4, 5, 6, 7] This will be elaborated on in section 2. Our analysis targets all BFs unlike work by others where a subset of the BFs are targeted [13, 14, 12]. This subset of BFs are extracted by analyzing the layout of the circuit based on the point defect assumption. This extraction process tries to enumerate the most likely faults. However, it suffers from some shortcoming viz, the layout is often not available; the process of fault extraction ....

F. J. Ferguson and J. P. Shen, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. on Comput.-Aided Design, Vol. 7, No. 11, pp. 1181 - 1194, 1988.

....manufacturers must ensure that shipped parts are actually good. To do this, manufacturers must test for the defects that are likely to occur. Shen, Maly, and Ferguson have performed defect simulation experiments showing that the majority of spot defects in MOS technologies cause shorts and opens [13, 23], and Feltham and Maly have shown that the majority of spot defects in current MOS technologies cause changes in the circuit description that result in shorts [11] The single stuck at fault model was adopted because it is powerful and simple, but it was never meant to represent the manner in ....

....in the presence of defects. A test set that detects 100 of single stuck at faults may not detect a high percentage of the manufacturing defects. Ferguson and Shen reported that complete single stuck at test sets failed to detect up to 10 of the probable shorts in the circuits they examined [13]. The need for tests that detect the electrical behavior exhibited by shorts requires a bridging fault model. The first step to generating bridging fault tests is to decide for which of the approximately n 2 potential bridging faults to target (where n is the number of nodes in the circuit) ....

F. J. Ferguson and J. P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988.

....that the test set detect 99.8 of the manufacturing defects. If the yield is 75 , the test set must detect 99.93 of the defects. Recent evidence shows that many defects are not detected by test sets that detect all single stuck at faults (hereafter called complete SSF test sets) in some circuits [FS88, SM90, PRM90]. The studies reported by Ferguson and Shen, and Storey and Maly consisted of defect simulations to determine which circuit level defects were probable, followed by a fault simulation to find the defect coverage [FS88, SM90] The study by Pancholy, et al. involved fabricating easily diagnosable ....

.... faults (hereafter called complete SSF test sets) in some circuits [FS88, SM90, PRM90] The studies reported by Ferguson and Shen, and Storey and Maly consisted of defect simulations to determine which circuit level defects were probable, followed by a fault simulation to find the defect coverage [FS88, SM90]. The study by Pancholy, et al. involved fabricating easily diagnosable integrated circuits, testing them with a diagnostic test set, and applying a complete SSF test set to the faulty ICs. The complete SSF test set detected only 98.74 of the faulty blocks on the ICs fabricated by Pancholy, et ....

[Article contains additional citation context not shown here]

F. Joel Ferguson and John P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988.

.... using input sets that cover 100 of the single stuck at faults (such an input set is called a complete SSF test set) In a defect simulation experiment involving over 400,000 defects and two industrial standard cells, greater than 40 of the defects could not be modeled as single stuck at faults[4]. In the same set of experiments, half of the defects (those causing electrical shorts between adjacent circuit nodes) were fault simulated with a complete SSF test set provided by the circuits manufacturer: At least 10 of the bridges were not detected by the complete SSF test set. If only the ....

....an I DDQ test for a specific fault includes first applying appropriate inputs to the circuit to cause excessive I DDQ , and then measuring I DDQ . Defect simulation experiments show that the vast majority of all local defects in MOS technologies cause bridges, breaks, and transistor stuck ons[16,4]. Some bridges, breaks, and transistor stuck ons are detectable as logical faults, although they may not be detected by specific complete SSF test sets, but others are only detectable as parametric faults. Defects can be undetectable as logical faults and still cause an IC to be unacceptable for ....

[Article contains additional citation context not shown here]

F. Joel Ferguson and John P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988.

....simple. When the SSA model was developed, the primary fabrication technology was TTL. In TTL logic, many defects do indeed manifest themselves as a logical stuck fault. Unfortunately, many of the defects that can occur in current CMOS processes are not manifested as logical stuck at faults [FS88] 2.3.2 Bridge Fault Models In bipolar logic, break faults tend to cause signal wires to be stuck at a specific logic value. Bridge faults do not have that effect and may not show up as stuck at faults. The resulting logic value of the wires being bridged together can usually be determined by ....

....a high percentage of the possible defects is very important for low defect levels. Since traditional fault models do not take defects into account at all, it is unlikely that tests generated from those fault models will consistently detect enough defects to ensure adequate quality levels [FS88] The last two bridge fault models presented 11 Spot Defect Conducting Regions Figure 2.4: Example of a defect causing a bridge fault. in the previous section dealt with defects directly, but in order for those models to be feasible, the list of possible defects for the IC must be known. ....

F. Joel Ferguson and John P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988.

....faults is generated using a defect simulation on the physical design of the circuit, only the realistically possible faults are reported. The defect simulations in IFA showed that over 99 of all the defects in a group of CMOS circuits caused circuit faults that were either bridge or break faults [5]. 2 Carafe The IFA process was shown feasible by the FXT software [5] However, FXT was primarily a research tool and was not intended to be used as general purpose IFA software. The goal of Carafe is to provide a robust and stable implementation of the defect simulation and defect to circuit ....

....the circuit, only the realistically possible faults are reported. The defect simulations in IFA showed that over 99 of all the defects in a group of CMOS circuits caused circuit faults that were either bridge or break faults [5] 2 Carafe The IFA process was shown feasible by the FXT software [5]. However, FXT was primarily a research tool and was not intended to be used as general purpose IFA software. The goal of Carafe is to provide a robust and stable implementation of the defect simulation and defect to circuit fault translation aspects of IFA in an easy to use software package. ....

F. Joel Ferguson and John P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988.

....yield requires that the test set detect 99.8 of the manufacturing defects. If the yield is 75 , the test set must detect 99.93 of the defects. Recent evidence shows that many defects are not detected by test sets that detect all single stuck at faults, or complete SSF test sets, in some circuits [FS88, SM90, PRM90]. The studies reported by Ferguson and Shen, and Storey and Maly consisted of defect simulations to determine which circuit level defects were probable, followed by a fault simulation to find the defect coverage [FS88, SM90] The study by Pancholy, et al. involved fabricating easily diagnosable ....

.... single stuck at faults, or complete SSF test sets, in some circuits [FS88, SM90, PRM90] The studies reported by Ferguson and Shen, and Storey and Maly consisted of defect simulations to determine which circuit level defects were probable, followed by a fault simulation to find the defect coverage [FS88, SM90]. The study by Pancholy, et al. involved fabricating easily diagnosable integrated circuits, testing them with a diagnostic test set, and applying a complete SSF test set to the faulty ICs. The complete SSF test set detected only 98.74 of the faulty blocks on the ICs. Our approach for increasing ....

[Article contains additional citation context not shown here]

F. Joel Ferguson and John P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Design, 7(11):1181--1194, November 1988.

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F. J. Ferguson and J. P. Shen, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. on Computer-Aided Design, Nov. 1988, pp. 1181-1194.

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