D. Felthaam and W. Maly, "Physically realistic fault models for analog CMOS neural networks," IEEE J. Solid-State Circuits, vol. 26, pp. 1223--1229, Sept. 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of fault extraction rules. In the fault extraction rules file, geometrical rules for fault extraction are given for each defect type, as well as the statistical defect density and size distributions (characterized for fault weighting) The defect density statistics are similar to the ones given in [23, 21]. The extracted faults are shorts and opens with different topologies and weights. After fault extraction, an histogram of fault weights is plotted, in order to study the distribution of weights. As it will be shown, this distribution widely influences the fault coverage results. Switch level ....

W. Maly. "Physically Realistic Fault Models for Analog CMOS Neural Networks". IEEE J. SolidState Circuits, 26(9):1223--1229, Sep. 1991.

....simulator to analyze real faults in digital circuits at the gate level for the purpose of fault grading. Our fault simulator will report a true fault coverage by considering the real faults and thus improves the yield factor when chips are actually tested by the test equipments. Feltham and Maly [17] demonstrated that many defects in modern CMOS technologies cause changes in the circuit description that result in electrical shorts and implied that many failures can be modeled by bridging faults. What differentiates our model from [17] or similar approach such as [11] and [18] is in: a) ....

....actually tested by the test equipments. Feltham and Maly [17] demonstrated that many defects in modern CMOS technologies cause changes in the circuit description that result in electrical shorts and implied that many failures can be modeled by bridging faults. What differentiates our model from [17] or similar approach such as [11] and [18] is in: a) considering resistive stuck at faults in addition to bridging faults, b) using an analytical fuzzy based analysis instead of lookup tables for accurate voltage computation, and c) generating test patterns using the resistance value of faults. ....

D. Felthaam and W. Maly, "Physically Realistic Fault Models for Analog CMOS Neural Networks," IEEE Journal of Solid-State Circuits, vol. 26, pp. 1223-1229, Sept. 1991.

....that the LSA model used for ATPG, although leading to a reasonably good coverage of bridging faults, does not lead to DL values as low as 100 ppm; hence, a new strategy needs to be developed. Failure mechanisms in present day CMOS process lines lead to the dominance of extra material failures [9], causing circuit shorts. Therefore, bridging faults [10, 11, 12] are also the main concern in this work. A significant research effort on the impact of bridging (BRI) faults has been carried out by different authors [10, 13, 14, 15, 16] aiming in particular at test pattern generation [11, 17, ....

D. Feltham, W. Maly, `Physically Realistic Fault Models for Analog CMOS Neural Networks', IEEE J. of Solid St. Circs., vol 26, no. 9, pp. 1223-1229, Sept., 1991.

....Level in an IC design environment. The methodology is based on the extension of the Williams Brown formula to non equiprobable faults [9,10] which are collected from the IC layout, by exploiting the concept of critical area, and using the information on a typical IC process line defect statistics [11]. Section 2 introduces the extension of equation (1) the concept of a weighting factor , associated with the probability of occurrence of each fault, and the de nition of a weighted fault coverage . The evaluation of the faults probabilitites, for di erent yield models, is presented in section 3, ....

D.B. Feltham, and W. Maly, Physically Realistic Fault Models for Analog CMOS Neural Networks, IEEE Journal of Solid State Circs. , vol. 26, no. 9, pp. 1223-1229, Sept., 1991.

....the break must occur in the interconnect wiring. In today s CMOS ICs with up to five metal layers, interconnect wiring is probably the most likely place for a break to occur. This is well supported by the critical area analysis by Xue, et al. 8] Also, vias are especially susceptible to breaks [9], and the number of vias exceeds the number of transistors in some microprocessor designs [10] We call the fault created by a break in the interconnect wiring an interconnect open. In order to make our terminology more specific, a break refers to a discontinuity caused by a manufacturing defect ....

....wire created by an interconnect open. straight metal track, we are not aware of any way of predicting where the open defect will land on this metal track. Besides, contacts are much more susceptible to opens than metal tracks are, according to the defect distribution statistics by Feltham and Maly [9]. Also, the increasing number of metal layers in IC processes tends to increase the number of vias per metal layer. In this work, each via, that produces a floating wire when broken, is considered to be a potential interconnect open defect site. The fault list for our simulator is produced by ....

D.B.I. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, Sep. 1991.

....tests only target single stuck at faults, which abstract defects as constant valued signals in the circuit. However, the majority of spot defects in current MOS technologies cause changes in the circuit description that result in shorts, which do not necessarily behave as single stuck at faults [FM91] Shorts between wires in the interconnect we define here as bridge faults. It is known that tests covering 100 of the testable single stuck at faults may not adequately cover bridge faults [MG91, FL91] 2 In spite of this shortcoming, tests targeted for single stuck at faults in practice ....

D. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, 26(9):1223--1229, September 1991.

....contains a wire that has lost its ability to change values. The wire is stuck at 1 or stuck at 0. The single stuck at fault model is widely used because of its simplicity [23] The majority of spot defects in modern CMOS technologies cause changes in the circuit description that result in shorts [11], which implies that many defects create bridging faults. The bridging fault model assumes that the outputs of two gates have been accidentally joined or bridged. Modeling the logic behavior of bridging faults is an option, but this 2 approach is complicated by the influence of relative drive ....

D. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, 26(9):1223--1229, September 1991.

.... the defect den1 Carafe Nemesis CShort Spice Hierarchical Carafe Short Behavioral Tables Cell Layouts Circuit Descriptions Test Patterns Circuit Layouts Defect Coverage Shorts Realistic Figure 1: The test pattern generation system for shorts within standard cells sities given by Feltham and Maly [FM91] In addition to using the standard version of Carafe on the individual cells, we also use a hierarchal version of Carafe on the entire circuit under test. The hierarchical version is designed to create a gate level description of the fault free circuit instead of a transistor level description. ....

D. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of SolidState Circuits, 26(9):1223--1229, September 1991.

....the break must occur in the interconnect wiring. In today s CMOS ICs with up to five metal layers, interconnect wiring is probably the most likely place for a break to occur. This is well supported by the critical area analysis by Xue, et al. 8] Also, vias are especially susceptible to breaks [9], and the number of vias exceeds the number of transistors in some microprocessor designs [10] We call the fault created by a break in the interconnect wiring an interconnect open. In order to make our terminology more specific, a break refers to a discontinuity caused by a manufacturing defect ....

....open is going to occur on a piece of straight metal track, we are not aware of any way of predicting where the open defect will land on this metal track. Besides, contacts are much more susceptible to opens than metal tracks are, according to the defect distribution statistics by Feltham and Maly [9]. Also, the increasing number of metal layers in IC processes tends to increase the number of vias per metal layer. In this work, each via, that produces a floating wire when broken, is considered to be a potential interconnect open defect site. The fault list for our simulator is produced by ....

D.B.I. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, Sep. 1991.

....a defect, which usually refers to the physical mechanism, such as an electrical short or open, that produces the incorrect behavior of the circuit. Feltham and Maly demonstrated that many defects in modern CMOS technologies cause changes in the circuit description that result in electrical shorts [19], which implies that many failures can be modeled by bridging faults [32] Intuitively, identifying a fault as the cause of a defect has much to do with the relative likelihood of certain defects occurring in the actual circuit. Inductive Fault Analysis [40] uses the circuit layout to determine ....

D. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, 26(9):1223--1229, September 1991.

....rules. The weighted critical area (WCA) is the critical area of a fault weighted by the probability of occurrence of the defect causing the fault. To obtain somewhat realistic WCAs from Carafe and Hemlock, we used defect distributions as reported for a typical digital CMOS fabrication technology[3]. The actual fabrication statistics file for Carafe and Hemlock was generated from that data and the Fabit program[7] Locations of the Short Causing Defects The data that we would like to see from these experiments are the percentages of the WCA of the shorts that fall into each of the ....

D. B. I. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, vol 26 no 9, pages 1223-1229. IEEE September, 1991.

....break needs to occur in the interconnect wiring. In today s CMOS ICs with five or more metal layers, interconnect wiring seems to be the most likely place for a break to occur. This is well supported by the critical area analysis by Xue, et al. 8] Also, vias are especially susceptible to breaks [9], and the number of vias is exceeding the number of transistors in some microprocessor designs [10] We call the fault created by a break in the interconnect wiring an interconnect open. In this paper, we describe a fault simulation algorithm for interconnect opens, that take into account all ....

....open is going to occur on a piece of straight metal track, we are not aware of any way of predicting where the open defect will land on this metal track. Besides, contacts are much more susceptible to opens than metal tracks are, according to the defect distribution statistics by Feltham and Maly [9]. Also, the increasing number of metal layers in IC processes tends to increase the number of vias per metal layer. In this work, each via, that produces a floating wire when broken, is considered to be a potential interconnect open defect site. The fault list for our simulator is produced by ....

D.B.I. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, Sep. 1991.

....diagnoses than that of traditional stuck at diagnosis. 1 Introduction Accurate fault diagnosis of realistic defects is an integral part of failure analysis. The majority of spot defects in modern CMOS technologies cause changes in the circuit description that result in electrical shorts [9], which implies that many failures are bridging faults [16] However, most fault diagnosis techniques use the single stuck at fault model to diagnose faulty ICs. Diagnosing bridging faults with single stuck at fault information is an appealing idea, but this approach can lead to unusably large ....

D. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, 26(9):1223--1229, September 1991.

.... have performed defect simulation experiments showing that the majority of spot defects in MOS technologies cause shorts and opens [13, 23] and Feltham and Maly have shown that the majority of spot defects in current MOS technologies cause changes in the circuit description that result in shorts [11]. The single stuck at fault model was adopted because it is powerful and simple, but it was never meant to represent the manner in which circuits behave in the presence of defects. A test set that detects 100 of single stuck at faults may not detect a high percentage of the manufacturing defects. ....

D. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, 26(9):1223--1229, September 1991.

No context found.

D. Felthaam and W. Maly, "Physically realistic fault models for analog CMOS neural networks," IEEE J. Solid-State Circuits, vol. 26, pp. 1223--1229, Sept. 1991.

No context found.

D. Feltham and W. Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, 26(9):1223--1229, September 1991.

No context found.

Derek Feltham and Wojciech Maly. Physically realistic fault models for analog CMOS neural networks. IEEE Journal of Solid-State Circuits, 26(9):1223--1229, September 1991.

No context found.

D. Feltham and W. Maly, "Physically Realistic Fault Models for Analog CMOS Neural Networks," IEEE Journal of Solid-State Circuits, vol. 26, pp. 1223-1229, Sept. 1991.

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