F. Brglez and H. Fujiwara, A Neutral Netlist of 10 Combinatorial Benchmark Circuits, IEEE Int. Symp. on Circuits and Systems, 1985  Home/Search   Document Not in Database   Summary   Related Articles   Check

....to compute the initialization values for an adder based TPG. 6] still deals with adder based accumulator structures, and is able to compute seeds so that the resulting test sequences obtain complete fault coverage for all the ISCA S85 circuits and the combinational parts of the ISCAS 89 circuits [9][10] 7] 8] present a universal algorithm called GATSBY (Genetic Algorithm based Test Synthesis tool for BIST applications) to compute the initialization values for a generic module used as TPG. Different test pattern generators were evaluated taking into account the parameters test length, ....

....and fixed equal for all the triplets of T. As TPGs, we focus on three accumulator based units including arithmetic functions such as adder, multiplier and subtracter, which are quite common in the actual SoCs. As UUT we consider the ISCAS 85 and the fullscan version of ISCAS 89 benchmark circuits [9][10] which are not random testable by 10k patterns. Final reseeding solutions are collected in Table 1, whereas Table 2 and Figure 2 allow a deeper analysis of the results. Experiments were run on a Sun SparcStation 5 110 with 64Megabytes of RAM. Table 1 reports the cardinality of the reseeding ....

F. Brglez and H. Fujiwara, A Neutral Netlist of 10 Combinatorial Benchmark Circuits, IEEE Int. Symp. on Circuits and Systems, 1985

....coverage but test length minimization. The method presented in [23] also applies to adderbased accumulator structures, and is able to compute seeds so that the resulting test sequences obtain complete fault coverage for all the ISCA85 circuits and the combinational parts of the ISCAS89 circuits [24][25] The performance of this method is in general better in terms of test length and number of seeds than the LFSR based reseedings. The serious drawback of this technique is the restriction to adder based structures. It is not expected that this limitation will generally be overcome in the ....

....a Program Control Unit, and memory) A block diagram is shown in Figure 5. In the next subsection we investigate the ability of the embedded functions, such as the ALU or the multiplier to test external units under test, which are connected to one of the buses. As UUTs, a subset of the ISCAS 85 [24] and ISCAS 89 [25] full scan version) benchmarks circuits that are not randomly testable by 10K patterns has been considered. A programmable, bus organized system as shown in Figure 9 has the advantage that memory is available and randomly accessible for storing the triplets for reseeding. If ....

F. Brglez and H. Fujiwara, A Neutral Netlist of 10 Combinatorial Benchmark Circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems, 1985

....the potential of our scheme in the domain of combinatorial circuits. This domain is frequently used as an application area in both probabilistic and deterministic reasoning [18, 40, 16] We analyze 11 benchmark combinatorial circuits widely used in the fault diagnosis and testing community [6] (see Table 1 ahead. For each circuit, the analysis is summarized in a chart displaying the time space complexity tradeo#s for diagnosing that circuit. The analysis allows tailoring the hybrid of tree clustering and cycle cutset decomposition to the available memory. Di#erent variants of the ....

....structural parameters of clustering and cutset on real life instances. Two, to gain further understanding of how space time tradeo# can be exploited to alleviate space bottlenecks. We analyzed empirically benchmark combinatorial circuits, widely used in the fault diagnosis and testing community [6]. See Table 1. The experiments allow us to assess in advance the complexity of diagnosis and abduction tasks on those circuits, and to determine the appropriate combination of tree clustering and cycle cutset methods to perform those tasks for each instance. None of the circuits are trees and ....

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Brglez and Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in fortran. In Proceedings of the IEEE International Symposium on Circuits and Systems, 1996.

....of faults currently addressed by the GA, but not covered by the best individual of the population. 4. Experimental Results The proposed algorithm has been implemented in ANSI C as a prototype tool named GATBSY. To assess the efficiency of the tool, experiments were performed on the ISCAS 85 [13] and the ISCAS 89 [14] full scan version) benchmarks, which are circuits not randomly testable by 10K patterns. The STPG is assumed having a state register size customized on the UUT input bits parallelism. In the present paper, the gate level ATPG Sunrise [15] is used to compute the fault list ....

F. Brglez and H. Fujiwara, A Neutral Netlist of 10 Combinatorial Benchmark Circuits, IEEE International Symposium on Circuits and Systems, 1985

....suffer. 5.3 A checking model experiment To illustrate the potential benefit of a checking model in an ATPG system, we present an experiment that compares the fault coverage of a model with and without independent verification. We used the Nemesis ATPG system [Lar92] on the ISCAS85 benchmarks [BF85] Nemesis attempts to cover faults with a combination of random vector simulation and deterministic ATPG. In addition, Nemesis rejects tests that could be invalidated because of feedback. For the generating model, we use the simplest bridge fault model available: wiredAND. For the checking model, ....

F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in fortran. In International Symposium on Circuits and Systems. IEEE, June 1985.

....Boolean difference method, but instead of performing symbol manipulation, it runs a Boolean Satisfiability algorithm on the formula. Nemesis, an ATPG system using the new method is quite practical: it correctly tests or proves untestable every fault in the ISCAS 85 (Brglez Fujiwara) benchmark set [3]. 2 The Boolean Satisfiability Method To generate a test pattern for a single fault, first extract a formula that defines the set of test patterns that detect the fault and then use a Boolean satisfiability algorithm to satisfy the formula. 2.1 Extracting the Formula A directed acyclic graph ....

....system as a whole as well as what kind of input we are using to evaluate Nemesis s performance. Nemesis is written in C and runs on a Sun Sparcstation 1 . We used the ten sample circuits collected by Franc Brglez and Hideo Fujiwara and distributed at the 1985 ISCAS Conference as input to Nemesis [3]. We used the Tegas Description Language (TDL) version of the ISCAS circuits. Before test pattern generation begins, Nemesis translates the TDL into an internal form and produces a collapsed fault list. After wirelist translation and fault collapsing, two phases of test pattern generation follow: ....

F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in fortran. In International Symposium on Circuits and Systems. IEEE, June 1985.

....discrepancies, make a cell that appears to be untestable, testable. Likewise, input discrepancies may combine with output discrepancies so that a fault is untestable. A discrepancy on an input wire can affect the detectability of 48 of the WCA in the layouts of the ISCAS 85 benchmark circuits [BF85] Faults representing 15 of the WCA in the commercial layouts of the ISCAS85 benchmark circuits cannot be tested without justifying discrepancies from the cell s input to a circuit output. Because of discrepancies on the inputs to faulted cells, it is also possible for a short to cause a ....

F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in fortran. In International Symposium on Circuits and Systems. IEEE, June 1985.

....travel through the front wire in the bridge. IV. Experimental Results Table 1 shows the number of stuck at faults, the number of Carafe extracted bridge faults, and the number of Primitive Bridge Functions associated with bridge faults for the MCNC layouts of the ten ISCAS 85 benchmark circuits [6]. Table 2 breaks bridge faults into 2 major categories: bridge faults that are capable of producing feedback and bridge faults that are not capable of producing feedback. Feedback bridge faults are subdivided into two groups. If, for a particular fault, every path from the back wire to a primary ....

F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in fortran. In International Symposium on Circuits and Systems. IEEE, June 1985.

....until the error is found. The method is fully described in [12] 4. Results A prototype diagnosis system implements the above algorithms in PROLOG, including the test pattern generator and the logic simulator. The software was applied to circuits taken from the ISCAS 85 and ISCAS 89 benchmarks [7, 6]. The results obtained on a SPARC 10 workstation with 10 Megabytes of memory are shown in Table 5 for combinational circuits , and Table 6 for sequential circuits. The columns titled No. of Exp. give, for each circuit, the number of diagnosis experiments made. Each experiment is made on a ....

F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in FORTRAN. In Proc. IEEE Int. Symp. Circuits and Systems, pages 663-- 698, June 1985.

....and, for feedback bridge faults, on feedback influenced values. 4 Results Table 1 shows the number of stuck at faults, the number of realistic bridge faults, and the number of Primitive Bridge Functions associated with the bridge faults for the MCNC layouts of the ISCAS 85 benchmark circuits [4]. There are 3 to 9 times as many bridge faults as there are stuck at faults for the given circuits with the MCNC layouts. Table 3 divides bridge faults into two categories: bridge faults that are capable of producing feedback and bridge faults that are not capable of producing feedback. Feedback ....

F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in fortran. In International Symposium on Circuits and Systems. IEEE, June 1985.

.... not prohibitive because only one PBF is needed for each type of fault block (and the number of different types will be small for synthesized layouts) Section 4 will compare numbers of stuck at faults, realistic bridging faults, and two component PBFs for the MCNC layouts of the ISCAS 85 circuits [6]. Carafe reports the likelihood of occurrence for each fault it extracts. This likelihood indicates how likely the fault is to occur relative to all of the other faults in the list. This means that the ATPG system can report not only what percentage of the realistic bridging faults are tested, but ....

F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in FORTRAN. In International Symposium on Circuits and Systems. IEEE, June 1985.

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