J.M. Acken, S.D. Millman, Accurate Modeling and Simulation of Bridging Faults, Proc. Custom Integrated Circuits Conference (CICC), pp 17.4.1 -- 17.4.4, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... 91] Storey 91] Perry 92] Gayle 93] Ma 95] In order to achieve the quality levels now required for digital integrated circuits, research has been done on deterministic test pattern generation and fault simulation techniques that explicitly target bridging faults [Abramovici 85] Acken 91] Millman 91] Lee 91] Ferguson 91] Hajj 92] Greenstein 92] Chess 93, 94] Rearick 93] Maxwell 93] While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo random testing of bridging faults. Pseudo random testing is an attractive ....

Acken, J.M., and S.D. Millman, "Accurate Modeling and Simulation of Bridging Faults," Proc. of 1991 Custom Integrated Circuits' Conference, pp. 17.4.1-17.4.4, 1991.

.... reality, not only do different gates have different thresholds, but each input of a gate has a different threshold [6] 7] It is well known that the stuck at fault model is inadequate for modeling bridging faults [8] 9] Many models have been developed for bridging faults [6] 10] 11] 12] 13] 14][15][16] Most of these fault models assume a zero ohm bridge resistance, but several models assume a resistive bridge [3] 17] 18] 19] 20] As shown in [1] many bridges can have significant resistance. Figure 1 shows the bridging resistance distribution fit to the data in [1] R b is the bridging ....

J. M. Acken and S. D. Millman, "Accurate Modeling and Simulation of Bridging Faults,". Cust. Int. Circ. Conf., 1991, pp. 17.4.4-17.4.4.

.... have recently been developed for handling conflicts that occur when the outputs of two gates are shorted and for predicting 2 the logic state at subsequent gates [5] 9] 13] Methods based on mixed mode simulation [9] precomputed tables containing data derived from analogue simulations [5] [6][11] 13] or extended switch level models [7] 10] can successfully handle a subset of bridging fault cases. Unfortunately, none of these approaches is applicable to situations of global feedback involving several logic gates that may result in asynchronous behavior or circuit oscillation. 2 ....

....of a sample out of a set of manufactured circuits. 3 In addition, Byzantine fault behavior means that an intermediate value within a certain interval may be interpreted as different logic values by different gates owing to the variation in threshold voltage between different gate types [2] 5][6][12] 13] Furthermore, as we use an extended switch level model, 10] with limited accuracy in comparison with electrical level analysis, to locally estimate the driving strength ratio between the two shorted nodes, we must assign a wider region. The U region of Figure 1 is therefore expanded to ....

J. M. Acken and S. D. Millman, "Accurate modeling and simulation of bridging faults", in Proc. IEEE Custom integrated Conf., 1991, pp. 17.4.1-17.4.4.

....two nets can be modeled by ANDing or ORing the logic values on the two nets [Mei 74] This is called the wired AND and wired OR model, respectively. However, bridges in CMOS technologies cannot be modeled as simple wired AND or wired OR logic; voting models are more accurate. In the voting model [Acken 91] when two nets driven to different logic levels are bridged together, the resolved logic level depends on the relative strengths of the pull up network (p transistors) and pull down network (n transistors) Although the voltage level of the bridged nets is a voltage divider between the pull up ....

Acken, J. M. and S. D. Millman, "Accurate Modeling and Simulation of Bridging Faults," in Proc. 1991 Custom Int. Circuits Conf., San Diego, CA, May 6--9, 1991, pp. 17.4.1--4.

....a reasonably good coverage of bridging faults, does not lead to DL values as low as 100 ppm; hence, a new strategy needs to be developed. Failure mechanisms in present day CMOS process lines lead to the dominance of extra material failures [9] causing circuit shorts. Therefore, bridging faults [10, 11, 12] are also the main concern in this work. A significant research effort on the impact of bridging (BRI) faults has been carried out by different authors [10, 13, 14, 15, 16] aiming in particular at test pattern generation [11, 17, 18] However, such research does not always consider physical ....

....fault. For each BRI, tabloid (1) identifies the nodes in conflict, 2) identifies the nodes of the logic elements whose outputs are in conflict (lo cal inputs) 3) creates a list with the local inputs logic values that activate the BRI (local vectors) and (4) defines the result of the voting [12] for each local vector. This result can be 1, 0 or X. The result of the voting is X if, as a consequence of the BRI, the voltage in the nodes involved, is in the uncertanty range. This uncertanty range is a consequence of different threshold voltages associated with the logic elements inputs. The ....

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J.M. Acken, S.D. Millman, "Accurate Modeling and Simulation of Bridging Faults", Proc. IEEE Custom Int. Circs. Conf., pp.17.4.1-17.4.4, 1991.

....addition, incorrect diagnoses might occur if the logic threshold values for gates driven by the output of one of the two bridged gates are not the same and if the logic levels for these gates are therefore interpreted di#erently. This scenario is referred to as the Byzantine Generals Problem [10] [11], 12] An alternative approach for fault diagnosis is to perform diagnostic fault simulation using information from the tester about failing outputs. This approach has been used in the past for single stuck at faults [13] During fault simulation, the actual output response of a failing device ....

J. M. Acken and S. D. Millman, "Accurate modeling and simulation of bridging faults," Proc. Custom Integrated Circuits Conf., pp. 17.4.1--17.4.4, 1991.

....the new function of the paired gates. These truth tables were minimized by Espresso and stored for use during the ATPG process. Assigning a logic value based on the inverter threshold is somewhat inaccurate in that it does not take into account the differing input thresholds for different gates[AM91]. We would have used a multi threshold ATPG system if one had been readily available. As we wanted to validate the general idea of being able to find undetectable shorts for the purpose of PDFT, fault simulation with a single threshold value was sufficient and provides more meaningful results than ....

J.M. Acken and S.D. Millman. Accurate modeling and simulation of bridging faults. Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1-- 17.4.4, 1991.

....test generation for bridges was new, the assumption that the bridges caused wired AND or wired OR behavior was fairly good. In the dominant technologies of the time (such as TTL) bridges did create wired logic. However, wired logic does not accurately reflect the behavior of static CMOS circuits [AM91, FL91, MG91] For a given CMOS cell library, it is not guaranteed that one of the nmos or pmos network will always determine the fault behavior. An example is shown in Figure 4.1, where the two bridged CMOS NAND gates from a commercial cell library produce a voltage that is not easily declared as ....

....that would 8 1 2.1V 0 0 0 Figure 4.1: A bridge fault which is not correctly modeled with wired logic be otherwise be logic 0. Correct modeling of the circuit s DC behavior involves determining an operating point with both a pmos path to power and a nmos path to ground. The voting model [Ack88, AM91] tries to find an operating point by examining the nmos and pmos transistor configurations, and calculating the equivalent conductances to power and ground. This is analogous to the two networks voting on the bridged node s output value. During actual simulation, the fault behavior is treated as ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. In Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

.... bridging faults 34 is two component simulation, in which the gates driving the bridged nodes are SPICE simulated to determine the bridge voltage, which is then compared against the SPICEcomputed logic thresholds of downstream gates in order to model the effect of the Byzantine Generals Problem [2, 3]. The simulator also extensively models feedback bridging faults. If a feedback bridging fault evidences the potential to oscillate or hold state, the simulator forces the bridge voltage to be the fault free value on the rear bridged node, thereby disallowing oscillation. Because the faulty ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. Proceedings of the Custom Integrated Circuits Confernce, pages 17.4.1--17.4.4, 1991.

....fault free gate outputs [1, 9, 12] These models are inaccurate for CMOS circuits, where the PBF will vary depending on the size, function, and technology of the bridged components. The voting model or an analog circuit analysis might be used to determine a more accurate Primitive Bridge Function [2, 3, 4]. It is possible that the inputs being driven by the bridged node may interpret the bridged voltage as different logic values because of different logic thresholds at the inputs [5] This paper explores the case where this factor does not contribute to the final outcome and the PBF can be ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. In Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

....idea of test generation for bridges was new, the assumption that the bridges caused wired AND or wired OR behavior was fairly good. In the dominant technologies of the time (such as TTL) bridges did create wired logic. However, wired logic does not accurately reflect the behavior of CMOS circuits [AM91, FL91, MG91]. In fact, the actual CMOS behavior is far enough from wiredlogic, that we must deal with voltages all the way from power to ground including voltages that may be interpreted by some gate inputs as a logic 0 and some as a logic 1; this is known as the Byzantine Generals problem [AM92] The ....

....model would assume that the circuit value at the fault site is described in general by a Boolean function of the inputs to the gates driving the bridged wires. This twocomponent model can be derived in a number of ways two notable methods are analog simulation [FL91, RP93] and the voting model [Ack88, AM91]. Two component simulation works well at modeling the upstream components from the fault site, but fails to take into account the possible sensitive behavior of downstream components. This oversight can be dealt with in two ways. An optimistic model assumes that the bridge value is always ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. In Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

....on layers separated by a single layer of insulating material [8, 9] Before generating tests for the realistic bridge faults, we must accurately model the change in logic function caused by the bridge. Because we are interested in defects in CMOS ICs, we cannot use a wired logic fault model [6, 2]. Instead, we replace a portion of the unfaulted circuit with a fault block in the faulted circuit. The function of the fault block depends on the behavior of the bridged components in the chosen technology. We call the logic function of the fault block the Primitive Bridge Function (PBF) of the ....

....the fault block can be determined, with varying degrees of accuracy, from resistive modeling A B C D Z X Y D C B A X Y Unfaulted Circuit Faulted Circuit Figure 1: A bridge fault creates a fault block. of the transistors [6] circuit analysis of the vote of transistors in series and in parallel [2], the tabular method used by Millmanand Garvey [12] or an analog circuit analysis of the two gates. Table 1 shows three possible PBFs for the introduced fault block from Figure 1. The column labeled ZWAND shows the fault block output if the technology in question follows the wired AND model, the ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. In Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

....subject to interpretation as different logic values by downstream logic gates. Because gate input logic thresholds are not identical, different downstream gates can interpret the voltage as different logic values: this phenomenon is known as the Byzantine Generals Problem [29] for bridging faults [3, 4]. Figure 2 shows a simple example of voltage interpretation in the presence of variable logic thresholds. This behavior has important implications for diagnosis: the propagation conditions for the error induced by a bridging fault are not necessarily the same as those caused by a stuck at fault. ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

....of the correct candidate, the candidate will no longer match and the diagnosis will fail. Our technique was highly successful at diagnosing bridging behaviors. However, variable logic thresholds downstream from the fault site (also known as the Byzantine Generals Problem for bridging faults [1, 2]) caused the diagnosis procedure to provide no candidate faults (an empty diagnosis) roughly ten percent of the time. The Byzantine Generals Problem is only the first of numerous details that can affect the behavior of real bridges. 2.2 Bridging Fault Modeling Predicting the behavior of bridging ....

....2.2 Bridging Fault Modeling Predicting the behavior of bridging faults in CMOS ICs is a difficult problem. Acken and Millmandemon2 strated that wired logic is a poor predictor of CMOS bridge behavior and suggested the voting model to take into account variable drive strengths in CMOS logic gates [1]. However, they pointed out that their method did not address the Byzantine Generals Problem for bridging faults [2] Maxwell and Aitken suggested biased voting as a solution to the Byzantine Generals Problem [19] but biased voting fails to simulate all the repercussions of feedback bridging ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

....five types: gate level, switchlevel, electrical level, mixed level, and table based. Gate level simulators ( 3, 4] to mention a few) employ either wired and or wired or logic to represent a BF so that the fault simulation can be done at the gate level speed. However, it was pointed out in [5, 6] that the circuit behavior under a BF could not be well modeled by permanent wired logic. Therefore a better BF modeling using the Primitive Bridge Functions (PBFs) was suggested. In general, the gate level methods have the following problems: 1. The circuit need to be structurally altered for ....

J. M. Acken and S. D. Millman, "Accurate modeling and simulation of bridging faults," IEEE Custom Integrated Circuit Conference (CICC), pp. 17.4.1--17.4.4, 1991.

....into the following five types: gate level, switch level, electricallevel, mixed level, and table based. Gate level approaches ( 11, 12] to mention a few) employ either wired and or wired or logic to model the bridged gates so that the BF simulation can be done efficiently at gate level. However, [13, 14] pointed out the inadequacy of using the wired logic models and suggested the use of Primitive Bridge Functions (PBFs) as better models to BFs. The PBFs are new gate primitives created by bridging the outputs of two gates. For each BF a PBF need to be placed into the circuit, therefore altering ....

J. M. Acken and S. D. Millman, "Accurate modeling and simulation of bridging faults," IEEE Custom Integrated Circuit Conference (CICC), pp. 17.4.1--17.4.4, 1991.

....is subject to interpretation as variable logic values by downstream logic gates. Because gate input logic thresholds are not identical, different downstream gates can interpret the voltage as different logic values: This phenomenon is known as the Byzantine Generals Problem for bridging faults [1, 2]. Figure 1 shows a simple example of voltage interpretation in the presence of variable logic thresholds. threshold: 2.4 V 2.5 V logic 1 logic 1 logic 0 logic 0 B A C threshold: 2.6 V Figure 1: An instance of the Byzantine Generals Problem for bridging faults. Each gate interprets the voltage as a ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. Proceedings of the Custom Integrated Circuits Confernce, pages 17.4.1--17.4.4, 1991.

.... Menon detailed complete theories and techniques to perform ATPG on bridging faults (including bridging faults that introduced feedback) in combinational circuits exhibiting wired logic behavior [1] However, wired logic does not accurately reflect the behavior of bridges in static CMOS circuits [4, 12, 20]. The wired logic model (wired AND or wired OR) is the easiest model to implement for simulation and test pattern generation; with the exception of feedback, the wired logic model is almost as easy for an ATPG system to deal with as the single stuck at model. A more exact model would assume that ....

....A more exact model would assume that the circuit value at the fault site is described in general by a Boolean function of the inputs to the gates driving the bridged wires. This function could be derived in a number of ways two notable methods are analog simulation [12, 22] and the voting model [3, 4]. Deriving the Boolean function by simulating the two components with the bridged outputs works well at modeling the upstream components from the fault site, but fails to take into account the possible sensitive behavior of downstream components. An optimistic model assumes that the bridge value ....

J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. In Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

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J.M. Acken, S.D. Millman, Accurate Modeling and Simulation of Bridging Faults, Proc. Custom Integrated Circuits Conference (CICC), pp 17.4.1 -- 17.4.4, 1991.

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J.M. Acken and S.D. Millman. Accurate modeling and simulation of bridging faults. Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1-17.4.4, 1991.

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J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. In Proceedings of the Custom Integrated Circuits Conference, pages 17.4.1--17.4.4, 1991.

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