John M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... incorrect assumption in CMOS circuits, where a bridge may result in a voltage on the affected nodes that may be interpreted as a logic 0 by some cell inputs and a logic 1 by other cell inputs (these are called indeterminate values) For CMOS non feedback bridge faults Acken s voting model is used[Ack88] to find the resulting logic values. The voting model states that when there is a bridge between nodes and each node is being driven to a different value, the resulting voltage is determined by a vote between the pullup path(s) and the pulldown path(s) where not all paths have the same ....

John M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....a single PMOS transistor is not. Note that the transistor strength model used in the COSMOS fault simulator cannot model this fault correctly by assigning any combination of strengths to the eight transistors. Bridger uses the resistive model for conducting transistors that was suggested by Acken [Ack88] and later by Storey[SM90] In experiments comparing the results of Spice simulations and Bridger, we found that if Bridger predicted the voltage at the bridged signals to be less than 2.0 Volts, Spice always predicted less than the logic threshold, and if Bridger predicted greater than 3.0 Volts, ....

John M.Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....either a logical fault or a delay fault. For ECL and TTL technologies it is assumed that the bridge fault behaves as a wired OR or wired AND. The logical behavior of a CMOS gate is often more complicated than this and is affected by transistor sizing, topology, and manufacturing process variations[17,1]. Whatever the logical function of the bridge fault, it may not be possible to meet the requirements for detection 3 This situation can be complicated by the existence of capacitive coupling between floating gates and adjacent nodes [17] 6 and a 0 in the faulty circuit D is a 1 in the good ....

John M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....Once the likely nonfeedback shorts were extracted from the physical design of the circuit, we determined their behavior. The two most commonly used methods of modeling shorts are the wired AND and wired OR models. However, neither of these adequately reflects the behavior of shorts in CMOS circuits[Ack88, FL91, MG91]. The logic value of shorted nodes is determined by how strongly each gate tries to force its value on the shorted node. Since the strength of a gate is generally a function of its inputs we must consider all inputs to the gates to determine what the actual logic value will be. We computed the ....

JohnM.Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....in the other. 2.2 Routing Modifications Another means of improving the testability of circuits is to modify the routing. In general, this is accomplished by separating lines to reduce the likelihood of undesirable shorts occuring. Several papers advocate improving testability through routing [Ack88, TTA 91, SCS 92, FKM92, Fer93] but little actual work has been done [MF94b, MF94a] 2.2.1 Routing and Placement Suggestions In his Ph.D. work, John M. Acken discussed reducing the likelihood of occurrence of shorts and increasing the testability of the shorts that do occur with routing ....

....TTA 91, SCS 92, FKM92, Fer93] but little actual work has been done [MF94b, MF94a] 2.2.1 Routing and Placement Suggestions In his Ph.D. work, John M. Acken discussed reducing the likelihood of occurrence of shorts and increasing the testability of the shorts that do occur with routing [Ack88] He suggests that outputs of multi input gates should be adjacent to as few other lines as possible. The more inputs a gate has, the harder it is to control. If a short occurs between two lines that are difficult to set to different values, the short may be hard to detect. Acken also suggests ....

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John M.Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....a node that would 8 1 2.1V 0 0 0 Figure 4.1: A bridge fault which is not correctly modeled with wired logic be otherwise be logic 0. Correct modeling of the circuit s DC behavior involves determining an operating point with both a pmos path to power and a nmos path to ground. The voting model [Ack88, AM91] tries to find an operating point by examining the nmos and pmos transistor configurations, and calculating the equivalent conductances to power and ground. This is analogous to the two networks voting on the bridged node s output value. During actual simulation, the fault behavior is ....

J. M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

.... the testability of shorts that do occur, by making the outputs of multiinput gates be adjacent to as few other lines as possible, keeping signals in different pseudo exhaustive testing segments from being adjacent, and giving preference to routing layers that are less susceptible to shorts [16]. Teixeira et al. suggested dividing realistic faults into fault classes based upon their resistance to stuck at test sets [17] and in their paper Work was done while at the Univercity of California Santa Cruz. that extended this work for bridging faults, Saraiva et al. proposed identifying ....

....large values of n. One technique to take advantage of exhaustive testing without requiring as many tests is to divide a circuit into segments that each have fewer inputs and to then exhaustively test each segment [34 39] This is referred to as psuedo exhaustive testing. As was mentioned by Acken [16], detectable BFs may go undetected by a psuedo exhaustive test set if the BF occurs between lines that do not have a segment in common. However, if they share at least one segment, the proper input combination will be exercised since all combinations of inputs to the segment will be exercised. ....

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J. M. Acken, Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....and a logic 1 by other cell inputs (these are called indeterminate values) Recent research in test pattern generation for bridge faults has focussed on obtaining a more accurate model of the logic value resulting from the bridge. For CMOS non feedback bridge faults Acken s voting model is used[Ack88] The voting model states that when there is a bridge between nodes and each node is being driven to a different value, the resulting voltage is determined by a vote between the pullup path(s) and the pulldown path(s) where not all paths have the same strength. An example of the voting model ....

John M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....bridging faults using relatively simple stuck at information, a desirable feature considering the expense of realistic fault models. 3. 1 MMA theory The MMA diagnostic theory, described below, followed from some relatively simple observations about bridging fault behavior under the voting model [2]. If Vector v detects a bridging fault in a CMOS circuit, the two bridged nodes necessarily have opposite fault free logic values when v is applied. The driving transistor networks of these two nodes will each attempt to assert competing logic values on the bridge. The application of v causes the ....

J. M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....a single PMOS transistor is not. Note that the transistor strength model used in the COSMOS fault simulator cannot model this fault correctly by assigning any combination of strengths to the eight transistors. Bridger uses the resistive model for conducting transistors that was suggested by Acken [Ack88]. In experiments comparing the results of Spice simulations and Bridger, we found that if Bridger predicted the voltage at the bridged signals to be less than 2.0 Volts, Spice always predicted less than the logic threshold, and if Bridger predicted greater than 3.0 Volts, Spice predicted greater ....

John M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....A more exact model would assume that the circuit value at the fault site is described in general by a Boolean function of the inputs to the gates driving the bridged wires. This function could be derived in a number of ways two notable methods are analog simulation [12, 22] and the voting model [3, 4]. Deriving the Boolean function by simulating the two components with the bridged outputs works well at modeling the upstream components from the fault site, but fails to take into account the possible sensitive behavior of downstream components. An optimistic model assumes that the bridge value ....

J. M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....fault free gate outputs [1, 9, 12] These models are inaccurate for CMOS circuits, where the PBF will vary depending on the size, function, and technology of the bridged components. The voting model or an analog circuit analysis might be used to determine a more accurate Primitive Bridge Function [2, 3, 4]. It is possible that the inputs being driven by the bridged node may interpret the bridged voltage as different logic values because of different logic thresholds at the inputs [5] This paper explores the case where this factor does not contribute to the final outcome and the PBF can be ....

J. M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.

....model would assume that the circuit value at the fault site is described in general by a Boolean function of the inputs to the gates driving the bridged wires. This twocomponent model can be derived in a number of ways two notable methods are analog simulation [FL91, RP93] and the voting model [Ack88, AM91]. Two component simulation works well at modeling the upstream components from the fault site, but fails to take into account the possible sensitive behavior of downstream components. This oversight can be dealt with in two ways. An optimistic model assumes that the bridge value is always ....

J. M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford Univer8 sity, Department of Electrical Engineering, September 1988.

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