Fountain, T. (1987). Processor Arrays: Architectures and applications. Academic-Press, London.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and as the inner contours are associated to the holes of a component, we can use them to detect all the holes of an image. Our algorithm provides such informations and can be directly executed in parallel architectures well suited for image processing applications, such as CLIP, DAP and MPP [Fountain 87] Some previous works concerned with binary connectivity have been presented in the literature. In [Rosenfeld 82] some algorithms describe how to de1 Classifying binary image contours 2 termine and track borders in an image. In [Duff 86] global propagation has been introduced to count the number ....

....can be executed within time O(logN) for a NxN image [Klette 80] All the above operations are easily implemented in a parallel architecture such as CLIP, MPP and DAP. These processor arrays have some hardware flexibilities which allow the execution of local operations in a simple and fast way [Fountain 87] We can speedup the execution of the algorithm by detecting the contours, in time t, from the con 5 Neucimar J. Leite tours detected in time t Gamma 1, i.e. not always from the geodesic dilation of ffi Sigma. This consideration leads to the following procedure. step = 0 O , I , ffi Z = ....

T. J. Fountain, Processor Arrays - Architecture and Applications, Academic Press, London, 1987.

....parallel computer architectures proposed for image processing. Thanks to the geographic local organization of the pixels in an image as a two dimensional mesh, and to the regularity of most lowlevel computations, mesh based parallel architectures are quite popular for image analysis applications [12, 16]. Indeed they allow efficient implementations of basic neighbor based primitives (convolution, filtering, etc. However, the situation is more complex when dealing with higher level image analysis algorithms. Their objective is mainly to find structural information in an image, to ease higher ....

Fountain, T. J. Processors Arrays: Architecture and Applications. Academic Press, 1987.

....were integrated on the same chip. There was a large explosion of custom architectures, mostly based on processor arrays with a bi dimensional grid interconnection scheme since it was thought to be the best solution for image processing. Starting from the original ideas of Unger [31] Fountain [13] classied in chronological order the dierent research projects and implementations according to a three generation taxonomy. The early ILLIAC [5] and CLIP [12] machines belong to the rst generation, mainly devoted to low level image processing tasks. The second generation comprises systems such ....

Fountain, T. (1987) Processor Arrays: Architectures and applications. Academic-Press, London.

.... processor MOB LAB control panel Figure 2: The configuration of the vision system for Image Checking and Analysis) 7] is a full custom SIMD massively parallel system composed of a square matrix of 256 single bit PEs disposed on the nodes of a 2D mesh, each one with full 8 neighbors connectivity [15, 12, 17]. In the current prototype the Processor Array (PA) is composed of an array of 4 4 full custom ICs (1.5 m CMOS, 45 mm 2 , 35000 transistors) each of them containing a sub array of 4 4 PEs. Each PE has an internal memory composed of 64 bits; the image to be processed is thus stored in an ....

T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

....CfflRAM architecture, 2) a working 8Kbit prototype, 3) a full scale CfflRAM designed in a 4Mbit DRAM process, and (4) CfflRAM applications. Introduction Massively parallel SIMD computers have been used for computationally intensive tasks for a some time. These SIMD machines include the AMT DAP [1], Goodyear s MPP [2] Thinking Machine s Connection Machine [3] and MasPar s MP 1 [4] These machines (presumably for ease of design and manufacture) partition the processing elements (PEs) and memory into separate chips. With this division, the number of PEs which can be integrated on a chip is ....

Terry Fountain. Processor Arrays: Architecture and Applications. Academic Press, 1987.

....tradeoffs. It also discusses the relationship between parallel architectures and algorithms. The discussion focuses on the control organization aspects of the relationship between architecture and algorithm; there are many more general discussions available in literature [ Cypher and Sanz, 1994, Fountain, 1987, Hord, 1990, Hord, 1993, Jamieson et al. 1987 ] 2.1 Parallel Algorithms Parallel processing is the cooperation of several tasks on solving a large problem concurrently [ Fox, 1988, Fox and Angus, 1990, Jamieson et al. 1987 ] The move from serial processing to parallel processing introduces ....

T. Fountain. Processor Arrays: Architecture and Applications. Academic Press, Orlando, FL, 1987.

....hierarchical non mesh data structures; ffl to provide a low cost experimental tool for research in the fields of image processing, VLSI design automation, and neural algorithms. The kernel of the system is a bidimensional mesh of single bit Processing Elements (PE) with a direct 8neighborhood [7]. The instruction set can be described in terms of mathematical morphology operators [16] augmented with logical operations. Control flow operations are defined over the entire SIMD mesh, and This work was partially supported by CNR Progetto Finalizzato Trasporti under contracts 93.01813.PF74, ....

....topology. In fact this latter must be defined also in combination with the processor instruction set and the mechanisms devoted to the management of data interchanges inside the system. Some examples of the data hierarchy of existing parallel architectures are shortly described below [7, 2, 17]: ffl hypercubes (N cubes) their memory ML is a flat data structure (D = 1) The dimension N 1 = N coincides with that of the cube. The parallelism C 1 defines the size (in bits) of each processor memory. Frame corners are F 1 i;min = 0 and F 1 i;max = 1, for every i 2 [1 : N ] ffl ....

T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

....the PA is composed of an array of 4 Theta 4 full custom ICs (1.5 m CMOS, 45 mm 2 , 35000 transistors) each of them containing a sub array of 4 Theta 4 PEs. In the present implementation, the PA is a 16 Theta 16 square matrix of 1 bit PEs each one with full 8 neighbors connectivity [9, 6, 11]; each PE has an internal memory composed of 64 bits; Image Memory 64 bit Processor Array Processor Array Internal Registers Image Window Data Bus 16 16 16 bit Figure 1: The logical organization of the first PAPRICA prototype data flow between the IM and the PA through a 16bit data bus. A block ....

T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

.... di Torino, Italy [5] PAPRICA is a massively parallel SIMD computer architecture devoted to the processing of 2D data structures; it is composed of a square matrix of 256 single bit Processing Elements (PEs) disposed on the nodes of a 2D mesh, each one with full 8 neighbors connectivity [9, 7, 12]. In the current prototype the Processor Array is composed of an array of 4 Theta 4 full custom ICs (1.5 m CMOS, 45 mm 2 , 35000 transistors) each of them containing a sub array of 4 Theta 4 PEs. Each PE has 64 internal registers. The PAPRICA low level processor, integrated on a single VME ....

T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

....data structure (Rosenfeld, 1984; Ballard Brown, 1982; Tanimoto Kilger, 1980) comprising the same image at different resolutions. Many different architectures have been developed recently to support this computational paradigm (Cantoni Ferretti, 1993; Cantoni, Ferretti, Savini, 1990; Fountain, 1987; Cantoni Levialdi, 1986) where the computing architecture contains a number of processing elements which is smaller than the number of image pixels and an external processor virtualization mechanism (Broggi, 1994) is used. A useful side effect due to resolution reduction is a decrease in the ....

Fountain, T. (1987). Processor Arrays: Architectures and applications. Academic-Press, London.

.... The PAPRICA (PArallel PRocessor for Image Checking and Analysis) project (Gregoretti, Reyneri, Sanso e, Rigazio, 1992; Conte, Gregoretti, Reyneri, Sanso e, 1991) was started in late 1988 in order to evaluate the application of massively parallel architectures (NCR Corporation, 1984; Fountain, 1987; Reddaway, 1973) and of mathematical morphology (Serra, 1982) to a number of tasks related to the verification at the layout level of integrated circuits. As a second step it was decided to build a prototype of an architecture with a bidimensional interprocessor connection as a coprocessor of a ....

....the complete recognition and description process can take place only at high resolutions, allowing the identification even of small details, thanks to the preliminary results obtained at a coarse resolution. These considerations lead to the use of a pyramidal data structure (Ballard Brown, 1982; Fountain, 1987), supported by PAPRICA system, consisting of the same image at different resolutions. Furthermore, it is important to note that in the case when the computing architecture contains a number of PEs smaller than the number of image pixels (namely when a PE virtualization mechanism (Broggi, 1994) is ....

Fountain, T. (1987). Processor Arrays: Architectures and applications. Academic-Press, London.

....power by exploiting parallelism on several parallel processors. Due to the rapid advance of VLSI technology in recent years, the manufacturing of parallel computers in large scale becomes feasible, giving an opportunity for many designers to build massively parallel processing systems [1, 2, 3, 4, 5]. 1 Research supported by RIST, ETRI and KOSEF There have been proposed various types of parallel architectures. However, each of them has its own merit and it is very difficult to decide which one to use. On the other hand, it is improper to purchase several parallel processing systems due to ....

T. Fountain, Processor Arrays: Architecture and Applications, Academic Press, 1987.

....a high number of PEs devoted to the simultaneous elaboration of a single image area. A number of processor arrays with a bidimensional grid interconnection scheme and a SIMD processing paradigm have been conceived, designed and implemented, starting from the original ideas of Unger [37] Fountain [11] has classified in chronological order the different research projects and implementations according to a three generation taxonomy. The early ILLIAC [3] and CLIP [26] machines belong to the first generation, mainly devoted to low level image processing tasks. The second generation comprises ....

T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

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Fountain, T. (1987). Processor Arrays: Architectures and applications. Academic-Press, London.

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T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

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T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

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T. Fountain. Processor Arrays: Architectures and applications. Academic-Press, London, 1987.

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T.Fountain, Processor Arrays Architecture and Applications, Academic Press, London, 1987.

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T. J. Fountain: "PROCESSOR ARRAYS: Architecture and Applications, " Academic Press, (June 1987)

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