S. Y. Kung et al., VLSI and Modern Signal Processing. Englewood Cliffs, NJ: Prentice Hall, 1985.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... propagation delay is given as a function of supply voltage threshold voltage load capacitance oxide capacitance per unit area electron mobility and the CMOS gate width to length ratio (2) Also, for a given technology, the time required to complete a bit bit multiplication can be approximated as [24], 25] 3) where is the delay of a one bit adder in units of seconds bit, and and are the level of data and reference quantization, respectively. Combining (1) and (2) gives (4) where and have been merged to form the parameter a technology dependent constant with units of volt seconds bit. The ....

S. Y. Kung et al., VLSI and Modern Signal Processing. Englewood Cliffs, NJ: Prentice Hall, 1985.

....SRDFG as shown in Fig. 13(b) is constructed by the node degeneration procedure. This graph consists of only 9 nodes, 18 edges, and 10 delays. 7 Experimental Results The CPU time to determine the iteration bound for practical SRDFGs are compared. We chose the 5th order elliptic wave filter (EWF) [14] and the recursive part of the 4 level pipelined lattice filter (PLF) 15] as benchmarks. EWF which consists of 34 nodes, 56 edges, and 7 delays is an SRDFG where the number of delays, jDj, is relatively smaller than the number of nodes, jN j, and the number of edges, jEj. On the other hand, PLF ....

S. Y. Kung, H. J. Whitehouse, and T. Kailath, VLSI and Modern Signal Processing. Englewood Cliffs, NJ: Prentice Hall, 1985.

....SRDFG as shown in Fig.6(b) is constructed by the node degeneration procedure. This graph consists of only 9 nodes, 18 edges, and 10 delays. 6 Experimental Results The CPU time to determine the iteration bound for practical SRDFGs are compared. We chose the 5th order elliptic wave filter (EWF) [11] and the recursive part of the 4 level pipelined lattice filter (PLF) 12] as benchmarks. EWF which consists Table IComp arisonof IterationBound DeterminationAlgorithms CPU [mS] Method Time complexity Memory requirement EWF PLF NCD O(jN jjEj log jN j) O(jN j jEj) 25.2 a 1.00 c LPM ....

S. Y. Kung, H. J. Whitehouse, and T. Kailath, VLSI and Modern Signal Processing. EnglewoodCliffs, NJ: Prentice Hall, 1985.

....SRDFG as shown in Fig. 13(b) is constructed by the node degeneration procedure. This graph consists of only 9 nodes, 18 edges, and 10 delays. 7. Experimental Results The CPU time to determine the iteration bound for practical SRDFGs are compared. We chose the 5th order elliptic wave filter (EWF) [14] and the recursive part of the 4 level pipelined lattice filter (PLF) 15] as benchmarks. EWF which consists of 34 nodes, 56 edges, and 7 delays is an SRDFG where the number of delays, jDj, is relatively smaller than the number of nodes, jN j, and the number of edges, jEj. On the other hand, PLF ....

S. Y. Kung, H. J. Whitehouse, and T. Kailath, VLSI and Modern Signal Processing. Englewood Cliffs, NJ: Prentice Hall,

....method, 80 times speed up is achieved in deriving an optimal schedule. B. Benchmarks The proposed scheduling methods are applied to processing algorithms, such as 4th order Jaumann wave digital filter (JAU) 10] 16 point FIR filter (FIR) 11] and 5th order wave elliptic digital filter (WEF) [12]. The topology of the array used is shown in Fig. 7. The CPU times in second are summarized in Table I. Table I shows: the name of a processing algorithm; the specified iteration period T i; CPU time for the complete model; CPU time for the reduced model (RM) CPU time for the constrained model ....

S. Y. Kung, H. J. Whitehouse, and T. Kailath, VLSI and Modern Signal Processing. Englewood Cliffs, NJ: Prentice Hall, 1985.

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