D. P. Bhandarkar. Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organisation. Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS-IV, 310--319, 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... the complexity of building a machine and may increase the average number of clocks per instruction (CPI) There have been lot of studies related to instruction set and its usage [10, 2, 15] Also there are extensive studies done to compare performance between the instruction set of RISC and CISC [1]. The designers of RISC made extensive study related to the instruction set usage and arrived at the following conclusions [6] The frequently used addressing modes are displacement, immediate and register deferred and these represent 75 99 of the addressing modes used in a program. Further a ....

D. Bhandarkar and D. W. Clark. Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization. ACM, Proceedings of the 4th International Conference on ASPLOS, pages 310--319, 1991.

....benchmark, the only requirement is that a compiler exists to run the program codes on 21 each target machine. Once executable versions have been determined, performance is obtained by running the codes and measuring the elapsed time. Several studies using the SPEC approach have appeared [45, 66, 23]. The disadvantage of code oriented benchmarks, especially for massively parallel processors, is that the performance of a given task on a given processor is often highly algorithm dependent. More significantly, the best performance for a particular task is often affected by different algorithms ....

Bhandarkar, D., and Clark, D. W. Performance from architecture: Comparing a RISC and CISC with similar hardware organization. In Proceedings of the Fourth International Conference on Architectural Support of Programming Languages and Operating Systems (1991), pp. 310--319.

....9.2 Calibrating the emulator 117 of remote memory with increasing access times. The execution time of a program on a processor is usually expressed as a function of the processor clock cycle time (T clock ) the instruction count (N instr ) and the average number of cycles per instruction (CP I) [26, 88]: CPU time = N instr Theta CPI av Theta T clock (9:1) The three quantities in the above equation depend on one or more of the following factors: ffl the application program, i.e. the algorithm and the source program. ffl the processor architecture and its instruction set. ffl the memory ....

D. P. Bhandarkar. Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organisation. Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS-IV, 310--319, 1991.

....numbers. First, consider the results for tcp input. The DEC Unix trace is roughly 50 longer than the 80386 count. Such a code inflation is not uncommon when converting CISC code to RISC code, especially considering that the traced Alpha code does not have sub word loads and stores available [3]. Second, comparing the ipintr results, we notice that IP input processing on the Alpha appears to be more than a factor of four longer than on the 80386. We believe this to be more an artifact of how the counting was performed rather than a real difference. For example, the DEC Unix ....

D. Bhandarkar and D. W. Clark. Performance from architecture: Comparing a RISC and CISC with similar hardware organization. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 310--319.

.... on the chip can be used for a register file supporting the stack for procedure calls or by a cache [GM89] Although there has been considerable debate between this two architectures concerning the complexity of hardware [PD80] instruction set [CHJ 85, FMM87] compilers [Pat85] and performance [BC91], none of the both classes has yet been finally proved to be superior. Examples of contemporary general purpose architectures include the Motorola 68040 [EGL 90] and IBM 80486 [Sar89] on the CISC side and the SPARC architecture [AG92] and PowerPC [BUOO94] on the RISC side, respectively. Language ....

D. Bhandarkar and D. W. Clark. Performance from architecture: Comparing a RISC and a CISC with similar hardware organization. In Intl. Conf. on Architectural Support for Prog. Lang. and Operating Sys., ASPLOS-IV, Santa Clara, CA, Apr. 8-11, 1991, pages 310--319. SIGARCH Comput. Archit. News, Vol. 19(2), 1991.

....one could calculate the total time spent executing a particular VAX opcode by summing the histogram counts for all of that opcode s microinstructions. Many other useful statistics can be imagined. This monitor has been used for a host of measurements at Digital, some of which are reported in [2, 5], some of which have been used in the development of subsequent VAX processors, and some of which have been used to evaluate and tune software of various kinds. 5.3 Table of practical trinomials Table 3 describes trinomials useful for counters up to 64 bits in width. We think 64 bits is a big ....

D. Bhandarkar and D.W. Clark, "Performance from architecture: comparing a RISC and a CISC with similar hardware organization," in Proc. Fourth Int. Conf. on Arch. Support for Prog. Lang. and Op. Sys. (ASPLOS IV), Santa Clara, CA, April 1991, pp. 310-319.

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D. P. Bhandarkar. Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organisation. Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS-IV, 310--319, 1991.

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