A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....such that G 1 [G 2 = G. Owens described a biplanar drawing of the complete graph K n with cr 2 (K n ) 7n =1536 O(n ) One can define cr k (G) similarly for any k 2, making G a union of k subgraphs. Determining cr k (G) would have application to the design of multilayer VLSI circuits [1]; but perhaps the case k = 2 is the most interesting, and even this simplest case is little explored so far. Note that one always can realize cr 2 (G) by drawing the edges of G 1 and G 2 on two different sides of the same plane, while identical vertices of G 1 and G 2 are placed to identical ....

Aggarwal, A., Klawe, M., Shor, P., Multi-layer grid embeddings for VLSI, Algorithmica 6 (1991), 129--151.

....of a graph G, denoted by (G) is the minimum number of planar graphs, whose union is G. Thickness is one of the classical and standard measures of non planarity of graphs [9] Multilayer embedding appears naturally in applications, like printed circuit design [6] and multilayer VLSI layouts [1]. The thickness has been determined exactly only for complete graphs, almost all) complete bipartite graphs, hypercubes, and graphs of orientable genus 1 and 2. Computing the thickness is NP hard [4] For further results on thickness, see the survey papers [2, 5] Wessel [8] proved that ; ....

Aggarwal, A., Klawe, M., Shor, P., Multi-layer grid embeddings for VLSI. Algorithmica 6 (1991), 129-151.

....[2,10] and of interest in this paper orthogonal drawings [4,6,13,16,20 22,26,28,31,33,38 40] here the edges of the graph are drawn as polygonal chains composed of axis parallel segments. This style of drawing has applications in three dimensional VLSI circuit design (see for example [1,34]) The three dimensional orthogonal grM consists of grid points in three dimensional space with integer coordinates, together with the axis parallel grid lines determined by these points. A three dimensional orthogonal drawing of a graph positions each vertex at a unique grid point, and ....

A. Aggarwal, M. Klawe, P. Shor, Multilayer grid embeddings for VLSI, Algorithmica 6 (1) (1991) 129-151.

.... maximum degree six graphs have been studied in [3, 4, 6, 10 13, 17, 19, 21, 22, 33, 35 37] By representing a vertex by a grid box, 3 D orthogonal drawings of arbitrary degree graphs have also been considered; see for example [5, 8, 21] 3 D graph drawing has applications in VLSI circuit design [1, 2, 18, 23, 26] and software engineering [15, 16, 24, 25] for example. Note that there is some experimental evidence suggesting that displaying a graph in three dimensions is better than in two [28, 29] Drawings with many bends appear cluttered and are difficult to visualise. In VLSI layouts, bends in the ....

A. AGGARWAL, M. KLAWE, AND P. SHOR, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129--151, 1991.

....are both 2N . Theorem 6. Every loopless graph has an orthogonal drawing, which can be computed in O(m) time, with O(mn) bounding box volume and three bends per edge route. This algorithm is particularly appropriate for multilayer VLSI as there are no vertical edge segments ( cross cuts ) see [1]. 4 Conclusions and open problems In this paper we have provided matching upper and lower bounds for threedimensional orthogonal box drawings. In particular, we showed that any algorithm to create three dimensional orthogonal drawings that have bounded aspect ratios or are degree restricted ....

A. Aggarwal, M. Klawe, and P. Shor. Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

....[2, 10] and of interest in this paper orthogonal drawings [4, 8, 13, 17, 21 23, 27, 29, 34, 36, 41 43] here the edges of the graph are drawn as polygonal chains composed of axis parallel segments. This style of drawing has applications in 3 dimensional VLSI circuit design (see for example [1, 37]) The 3 dimensional orthogonal grid consists of grid points in 3 dimensional space with integer coordinates, together with the axis parallel grid lines determined by these points. A 3 dimensional orthogonal drawing of a graph positions each vertex at a unique grid point, and represents each edge ....

A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

....and with each edge assigned to a layer so that no two edges in the same layer cross. Geometric thickness was rst introduced under the name of real linear thickness by Kainen [17] and has recently been studied by Dillencourt et al. 11] Applications of geometric thickness include multilayer VLSI [1, 2] and graph visualization where layers correspond to colours in a drawing. Geometric thickness is closely related to the (graph theoretic) thickness of a graph, de ned to be the minimum number of subgraphs in a partition of the edges into planar subgraphs, denoted by (G) See [22] for a survey ....

A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

....with n vertices and m edges, and with at most b bends per edge. This paper establishes improved upper bounds on vol(n; m; 1) and vol(n; m; 2) A drawing with height k and with all vertices having height k is said to be in the k PCB (Printed C ircuit Board) model, as de ned by Aggarwal et al. [2]. Such drawings, which we call multilayer drawings, are an appropriate model for multilayer VLSI circuits. In multilayer VLSI, vertical edge segments between di erent Z planes, called cross cuts, lead to a deterioration in performance with an increase in the likelihood of faulty chips [2] ....

....et al. 2] Such drawings, which we call multilayer drawings, are an appropriate model for multilayer VLSI circuits. In multilayer VLSI, vertical edge segments between di erent Z planes, called cross cuts, lead to a deterioration in performance with an increase in the likelihood of faulty chips [2]. Therefore drawings without crosscuts are particularly desirable. In this paper we observe that for drawings with a xed maximum number of bends per edge, permitting cross cuts allows for drawings with less volume. We consider three types of multilayer drawings, which are de ned by the relative ....

A. Aggarwal, M. Klawe, and P. Shor. Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

....body of research in 3 dimensional graph drawing. In this paper we are interested in 3 dimensional orthogonal graph drawing; here the edges of the graph are drawn as polygonal chains composed of axisparallel segments. This style of drawing has applications in VLSI circuit design (see for example [1, 15]) Throughout this paper we consider n vertex m edge undirected graphs G, possibly with parallel edges but no loops, with vertex set V (G) and edge set E(G) The 3dimensional orthogonal grid consists of grid points in 3 dimensional space with integer coordinates, together with the axis parallel ....

....edge e = vw 2 E(G) with v w we de ne R(e) w and L(e) v; e is called a successor edge of v and a predecessor edge of w. As de ned above, the number of successor and predecessor edges of a vertex v are denoted by succ(v) and pred(v) respectively. The successor edges of v are denoted by v[1]; v[2] v[succ(v) where R(v[1] R(v[2] R(v[succ(v) The predecessor edges of v are denoted by v[ 1] v[ 2] v[ pred(v) where L(v[ pred(v) L(v[ pred(v) 1] L(v[ 1] Furthermore, we require the following consistent numbering of parallel ....

[Article contains additional citation context not shown here]

A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI, Algorithmica, 6(1991), 129-151.

....Lower and upper bounds are established for the geometric thickness of complete and complete bipartite graphs in [DEH00] In particular, it is shown that (Kn ) Kn ) for large n. On the other hand, K a;b ) K a;b ) when a b. Applications of geometric thickness include multilayer VLSI [AKS91] and graph visualisation [DETT99] Another parameter closely related to geometric thickness is that of book thickness. A book consists of a line in 3 space, called the spine, and some number of pages, each a halfplane with the spine as boundary. A book embedding of a graph consists of a linear ....

A. Aggarwal, M. Klawe, and P. Shor. Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

....graph drawing. Orthogonal graph drawing, where edges are routed along a rectangular grid, is a popular drawing style which is also appropriate for VLSI circuit layout. In this paper we study three dimensional orthogonal graph drawings. Such drawings have application in three dimensional VLSI; see [1,2,18,22,23]. We improve on previous results by generalising the existing lower bounds on the volume, and by giving new constructions with smaller volume. In fact, our upper and lower bounds are matching up to a constant factor, and hence asymptotically optimal. We give lower bounds and constructions for ....

....m, and the width and depth are both 2N . Theorem 6 Every loopless graph has a drawing, which can be computed in O(m) time, with O(mn) volume, and three bends per edge route. This algorithm is particularly appropriate for multilayer VLSI as there are no vertical edge segments or cross cuts ; see [2]. 4 Conclusions and open problems In this paper, we provided matching upper and lower bounds for the volume of three dimensional orthogonal box drawings, under various restrictions on the shape of vertex boxes. In particular, we showed that any algorithm to create three dimensional orthogonal ....

A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica 6(1) (1991), 129--151.

....complete and complete bipartite graphs. In practice, the planar crossing number appears in the fabrication of VLSI circuits [17] Producing drawings of graphs with a small number of crossings can influence the area of the layout as well as the number of wire contact cuts that should be minimized [1]. For this reason deriving asymptotic bounds for the planar crossing number has been popular in the VLSI community [17] Computing the planar crossing number of a graph has been known to be NP complete [8] A natural generalization of the planar crossing number is the crossing number of a graph on ....

Aggarwal, A., Klawe, M., and Shor, P., Multilayer grid embeddings for VLSI, Algorithmica, 6 (1991), 129--143.

....restricted to G i is a planar embedding of G i , for 1 # i # #(G) Note that the three subgraphs of K 9 in Figure 12 are drawn in a way so that the union of their embeddings does not yield a drawing of K 9 . Knowing the thickness of a given graph can be helpful in some application problems. AKS91] proposes two new multilayer grid models for VLSI layout and shows for one of them that a graph with n vertices and thickness 2 can be embedded in two layers in an area of size O(n 2 ) Furthermore, another algorithm embeds a graph with n vertices and thickness t in t layers in O(n 3 ) area, ....

Alok Aggarwal, Maria Klawe, and Peter Shor. Multilayer Grid Embeddings for VLSI. Algorithmica, 6:129--151, 1991.

....[2, 8] and of interest in this paper orthogonal drawings [3, 5, 12, 16, 20 22, 26, 28, 32, 33, 39 41] here the edges of the graph are drawn as polygonal chains composed of axis parallel segments. This style of drawing has applications in 3 dimensional VLSI circuit design (see for example [1, 34]) The 3 dimensional orthogonal grid consists of grid points in 3 dimensional space with integer coordinates, together with the axis parallel grid lines determined by these points. A 3 dimensional orthogonal drawing of a graph positions each vertex at a unique grid point, and routes each edge as a ....

A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

....body of research in 3 dimensional graph drawing. In this paper we are interested in 3 dimensional orthogonal graph drawing; here the edges of the graph are drawn as polygonal chains composed of axisparallel segments. This style of drawing has applications in VLSI circuit design (see for example [1, 15]) Throughout this paper we consider n vertex m edge undirected graphs G, possibly with parallel edges but no loops, with vertex set V (G) and edge set E(G) The 3dimensional orthogonal grid consists of grid points in 3 dimensional space with integer coordinates, together with the axis parallel ....

....each edge e = vw 2 E(G) with v w we de ne R(e) w and L(e) v; e is called a successor edge of v and a predecessor edge of w. As de ned above, the number of successor and predecessor edges of a vertex v are denoted by succ(v) and pred(v) respectively. The successor edges of v are denoted by v[1]; v[2] v[succ(v) where R(v[1] R(v[2] R(v[succ(v) The predecessor edges of v are denoted by v[ 1] v[ 2] v[ pred(v) where L(v[ pred(v) L(v[ pred(v) 1] L(v[ 1] Furthermore, we require the following consistent numbering of parallel edges. ....

[Article contains additional citation context not shown here]

A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI, Algorithmica, 6(1991), 129-151.

.... drawings of maximum degree six graphs have been studied in [7, 9 11, 15, 18, 19, 28] By representing a vertex by a grid box, 3 D orthogonal drawings of arbitrary degree graphs have also been considered [4 6, 12, 18, 29, 30] 3 D graph visualisation has applications in VLSI circuit design [1, 2, 17, 20, 23] and software engineering [13, 14, 21, 22] for example. Drawings with many bends appear cluttered and are difficult to visualise. In VLSI layouts bends in the wires increase the cost of production and the chance of circuit failure. Therefore minimising the number of bends, along with minimising ....

A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129--151, 1991.

....Research, 331 Mudd, New York, NY 10027, USA z Research Institute for Mathematical Sciences, Kyoto University, Kyoto 606, Japan contact cuts are used, the manufacturing cost measure of this method is the number of layers. An application of this approach was given by Aggarwal, Klawe and Shor [AKS91]. They proposed a layout algorithm with a provably good layoutarea. Since the algorithm needs a priori a decomposition of the graph in planar subgraphs, a graph theoretic treatment seems helpful. Indeed, both approaches have a graph theoretic counterpart. In the first one we look for the minimum ....

Aggarwal, A., M. Klawe, and P. Shor, Multilayer Grid Embeddings for VLSI, Algorithmica 1 (1991), 129--151.

....of G restricted to G i is a planar embedding of G i , for 1 i (G) Note that the three subgraphs of K 9 in Figure 13 are drawn in a way so that the union of their embeddings does not yield a drawing of K 9 . Knowing the thickness of a given graph can be helpful in some application problems. AKS91] proposes two new multilayer grid models for VLSI layout and shows for one of them that a graph with n vertices and thickness 2 can be embedded in two layers in an area of size O(n 2 ) Furthermore, another algorithm embeds a graph with n vertices and thickness t in t layers in O(n 3 ) ....

Alok Aggarwal, Maria Klawe, and Peter Shor. Multilayer Grid Embeddings for VLSI. Algorithmica, 6:129-151, 1991.

....densities achievable in vertex and edge connectivity PGA s decrease at different rates. Hence, the capability to connect more than one pair of wires at a switching node allows for a significant increase in density. The results of Sections 5 and 6 are related to those of [CS 78] AKLLW 85] and [AKS 89] These papers consider the minimal size of a grid that can embed planar graphs of size n with prescribed vertex locations. Ignoring slight model differences, their results show that in the model equivalent to vertex connectivity the grid has to be of size Theta(n 3 ) while in the model ....

....as the size of implementable circuits increases, the achievable densities in vertex and edge connectivity PGA s decrease at different rates. Switching nodes capable of simultaneously connecting two wire pairs significantly increase the achievable density. We do not describe the lower bound here. AKS 89] provided an algorithm for embedding a planar graph of size n in a grid of area O(n 3 ) with prescribed vertex locations. This algorithm can be modified easily to embed any planar graph of size k in a rectangular vertex connectivity PGA of area O(nk 2 ) with n processing nodes. The ....

A. Aggarwal, M. Klawe, P. Shor, `Multi-Layer Grid Embeddings for VLSI', to appear, Algorithmica.

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A. Aggarwal, M. Klawe, P. Shor, "Multi-layer grid embeddings for VLSI," Algorithmica, 6(1991), pp. 129--151.

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A. Aggarwal, M. Klawe, P. Shor, "Multi-layer grid embeddings for VLSI," Algorithmica, 6(1991), pp. 129--151.

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A. Aggarwal, M. Klawe, P. Shor, "Multi-layer grid embeddings for VLSI," Algorithmica, 6(1991), pp. 129--151.

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A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

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A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

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A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

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A. AGGARWAL, M. KLAWE, AND P. SHOR, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129--151, 1991.

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A. Aggarwal, M. Klawe, and P. Shor. Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129--151, 1991.

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A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-- 151, 1991.

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A. Aggarwal, M. Klawe, P. Shor, "Multi-layer grid embeddings for VLSI," Algorithmica, 6(1991), pp. 129--151.

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A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

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A. Aggarwal, M. Klawe, and P. Shor, Multilayer grid embeddings for VLSI. Algorithmica, 6(1):129-151, 1991.

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A. Aggarwal, M. Klawe, P.Sh9= Multilayer grid embeddings for VLSI,

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Aggarwal, A., Klawe, M., Shor, P., Multi-layer grid embeddings for VLSI, Algorithmica 6 (1991), 129--151.

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