F. Corella, J. M. Stone, and C. M. Barton. A Formal Specification of the PowerPC Shared Memory Architecture. Technical Report RC 18638(81566), IBM Research Division, T.J. Watson Research Center, January 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....performance. Researchers have proposed several approaches to relax the program order and atomicity constraints of sequential consistency. One common technique is to simply relax the consistency model by explicitly allowing out of order and non atomic execution of certain memory operations [14, 16, 17, 22, 35, 36]. Such models provide significant performance gains but require programmers to forgo the simple interface of sequential consistency. Furthermore, several relaxed models exist and often differ from each other in subtle but significant ways [3, 19] The variety and complexity of these models ....

....A more comprehensive coverage appears in [1] 7. 1 Work Motivated by Hardware and Runtime System Optimizations Several researchers have proposed relaxed memory consistency models that explicitly specify relaxations of the program order and atomicity requirements of sequential consistency (e.g. [17, 22, 25, 36, 35, 16, 11, 14]) A disadvantage of these models is that their system centric nature results in several different and complex interfaces for the programmer [3, 19] thereby complicating programmability and portability. To address the above disadvantages of the system centric relaxed models, researchers have ....

F. Corella, J. M. Stone, and C. M. Barton. A Formal Specification of the PowerPC Shared Memory Architecture. Technical Report RC 18638(81566), IBM Research Division, T.J. Watson Research Center, January 1993.

....concentrates on the other class of relaxed memory consistency models, including weak ordering and release consistency, that allows a processor to reorder reads and writes, provided that a processor sees its own reads and writes in order. Commercial models in this class include Alpha [30] PowerPC [9, 18], IA 64 [20] and SPARC Relaxed Memory Order (RMO) 33] These models differ in subtle ways, but they all require that the programmer insert one or more memory barriers (a.k.a. MBs, barriers, membars, fences, or syncs) or annotations to assert required orderings. Unlike with SC and PC, ....

....a memory barrier to enforce the ordering of two reads (even if the reads are data dependent) We say that the former models enforce data dependence order. We now discuss both alternatives in turn. Models that enforce data dependence. We first discuss models, including SPARC RMO [33] PowerPC [9, 18], and IA 64 [20] that require a memory barrier to order independent reads but not dependent reads. In the latter case, hardware is required to preserve the dependence order. Even without considering value prediction, programmers that want the linked list code to allow only the two expected ....

F. Corella, J. M. Stone, and C. M. Barton. A Formal Specification of the PowerPC Shared Memory Architecture. IBM Technical Report RC 18638, Jan. 4, 1993.

....this paper focuses on the last technique as further elaborated in Section 1.2. 1.1 Techniques to Relax Program Order and Atomicity Requirements Relaxed memory consistency models. Several relaxed memory consistency models have been proposed that allow out of order and non atomic memory operations [18, 20, 21, 28, 50, 51], and provide significant performance gains [25, 27, 53] The disadvantage of relaxed models, however, is that they require programmers to forgo the simple interface of sequential consistency; instead, programmers must deal with out of order and non atomic operations. Furthermore, several relaxed ....

.... including weak ordering [21] release consistency (RCsc and RCpc) 28] lazy release consistency [34] processor consistency [28] SPARC V8 total store ordering [51] SPARC V8 partial store ordering [51] SPARC V9 relaxed memory ordering [50] the Alpha model [15, 20] and the PowerPC model [18]. The models describe various relaxations of the program order and atomicity requirements of sequential consistency, thereby improving performance [25, 27, 53] A disadvantage of the above models is that their system centric nature results in several different and complex interfaces for the ....

F. Corella, J. M. Stone, and C. M. Barton. A Formal Specification of the PowerPC Shared Memory Architecture. Technical Report RC 18638(81566), IBM Research Division, T.J. Watson Research Center, January 1993.

....as well as branch predictions, and would support virtual synchrony. In particular, it would be interesting to merge the framework developed in [10] with the one developed here. It may also be interesting to apply this framework to recent commercial architectures, like DEC Alpha [1] and PowerPC [20], the way the framework of [10] is applied to the DEC Alpha in [12] This work did not address the issue of how the application program can deal with failures. This issue includes several important questions. For example, what to do with tasks that were executing on machines that crashed Do we ....

F. Corella, J. Stone, and C. Barton. A Formal Specification of the PowerPC Shared Memory Architecture. Technical Report Research Report #RC18638, IBM, 1994.

.... instructions TSO [20] p p RMW PC [13, 12] p p p RMW PSO [20] p p p RMW, STBAR WO [5] p p p p synchronization RCsc [13, 12] p p p p release, acquire, nsync, RMW RCpc [13, 12] p p p p p release, acquire, nsync, RMW Alpha [19] p p p p MB, WMB RMO [21] p p p p various MEMBAR s PowerPC [17, 4] p p p p p SYNC Figure 8: Simple categorization of relaxed models. A p indicates that the corresponding relaxation is allowed by straightforward implementations of the corresponding model. It also indicates that the relaxation can be detected by the programmer (by affecting the results of the ....

Francisco Corella, Janice M. Stone, and Charles M. Barton. A formal specification of the PowerPC shared memory architecture. Technical Report Computer Science Technical Report RC 18638(81566), IBM Research Division, T.J. Watson Research Center, January 1993.

....previous works in attempting to provide a formal memory model for an existing architecture and using this model to develop programming techniques for systems based on this architecture. The first is for the Stanford DASH multiprocessor [19, 20] and the second is for PowerPC based multiprocessors [12]. Gharachorloo, Gibbons and Merritt define release consistency, a formal definition of the memory model of the Stanford DASH multiprocessor. They show that PL programs run on release consistency as if it was sequentially consistent [19, 20] PL programs are similar to generalized data race free ....

....be indivisible atomic operations. In addition, PL programs require a pairing to be defined between release and acquire operations; alpha consistency does not impose a similar requirement. Corella, Stone and Barton provide an axiomatic definition of the memory model of PowerPC based multiprocessors [12]. They show that if all accesses to shared data on a PowerPC based multiprocessor are protected with lock unlock sequences, then the result is as if the hardware was sequentially consistent. Protecting all access with lock unlock sequences is a special case of generalized data race free programs; ....

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F. Corella, J. Stone, and C. Barton. A Formal Specification of the PowerPC Shared Memory Architecture. Technical Report Research Report #RC18638, IBM, 1994.

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F. Corella, J.M. Stone, and C.M. Barton, "A Formal Specification of the PowerPC Shared Memory Architecture," Tech. Report 18638, IBM T.J. Watson Research Center, Jan. 1993.

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