C. Tseng and D. P. Siewiorek. FACET: A procedure for automated synthesis of digital systems. In Proc. of the 20th Design Automation Conference, pages 566--572, June 1983.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....in the cdfg are turned into states with conditional transitions. Their transition conditions are supplied from the data path in the form of condition flags. Operator, register and interconnect allocation algorithms, which follow the scheduling step, are typically based on clique partitioning [50] or graph coloring [3] following life cycle analysis of the scheduled flow graph. Operator, register and interconnect allocation algorithms perform no code motion and do not alter the control flow. Their focus is essentially on resource sharing to meet cost (area) constraints. Binding refers to ....

....this relation. Appropriate register binding functions should be defined for each scheme. Accordingly, the verification strategies should be adjusted to account for these new binding relations. The carrier based register allocation scheme yields a mapping from the variables to the registers. FACET [50], HAL [38] and CHARM [56] use carrier based techniques for register optimization. Register optimization is only possible when two (or more) variables have non overlapping lifetimes, in which case they are bound to the same register. Therefore, the mapping from the specification variables to rtl ....

Tseng, C. and D. P. Siewiorek: 1983, `Facet : A Procedure for the Automated Synthesis of Digital Systems'. 20th ACM/IEEE Design Automation Conference.

....to a register module whose bit width is the maximum of the bit widths of all carriers in the group. Various register optimization strategies have been proposed [20] Our register optimization algorithm is based on a clique partitioning heuristic on the lines proposed by Tseng and Siewiorek [21]. Interconnect Optimization The goal of interconnect optimization is to assign an interconnect path to each value transfer in the dfg. Interconnect paths are formed using point to point wires, multiplexors and gated buses (buses whose drivers are enabled through transmission gates) Various cost ....

C. Tseng and D. P. Siewiorek, "Facet : A Procedure for the Automated Synthesis of Digital Systems," 20th ACM/IEEE Design Automation Conference, pp. 490-496, 1983.

.... resource allocation algorithm [20] Similarly, Chang and Pedram also consider the allocation of FUs of varying latency but their focus is on energy minimization [21] Clique based partitioning algorithms were developed in the FACET project to jointly minimize FU and inter FU communication costs [22]. In [16] greedy list scheduling techniques are presented that use bitwidth information during scheduling to select hardware units having compatible width. An additional problem of minimizing the cost of transmitting and extending operands of variable bitwidth has been addressed in [23] ....

C. Tseng and D. P. Siewiorek, "FACET: A procedure for automated synthesis of digital systems," in Proceedings of the 20th Design Automation Conference, pp. 566--572, June 1983. 41

....into the hardware components. Operation scheduling determines the hardware costspeed tradeoffs of a design. The simplest way to perform scheduling is to relegate the task to the user to explicitly define the parallelism of the design such as in the SLICE system [1] The FACET system, presented in [2], used ASAP schedule for finding near optimal solution. Conditional deferment methods, such as in [3] were based on the fact that if the operation concurrency is higher than the number of available units, those operations should be postponed. Another method to avoid too many resources in is list ....

....the interested readers to [20] VI. Experimental Results The MFS and MFSA algorithms have been implemented in C and integrated within a synthesis tool called SYNTEST [21] which produces a self testable RTL structure. This section presents results for seven design examples: 1) FACET introduced by [2], 2) MAHA, a) and (b) from [5] 3) Second order differential equation already used as an example in section 3 and 4 to describe our method, 4) Band pass filter chosen from [22] 5) Complex biquad recursive digital filter borrowed from [23] 6) Fifth order wave digital elliptical filter from [24] ....

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C. Tseng and D. P. Siewiorek, "FACET: A Procedure for the Automated Synthesis of Digital Systems," in Proc. 20th design Automation Conf., June 1983, pp. 566-572.

....the hardware components. Operation scheduling determines the hardware cost speed tradeoffs of a design. The simplest way to perform scheduling is to relegate the task to the user to explicitly define the parallelism of the design such as in the SLICE system [1] The FACET system, presented in [2], used ASAP schedule for finding near optimal solution. Conditional deferment methods, such as in [3] were based on the fact that if the operation concurrency is higher than the number of available units, those operations should be postponed. List scheduling techniques, such as in [4] sort and ....

C. Tseng and D. P. Siewiorek, "FACET: A Procedure for the Automated Synthesis of Digital Systems," Proc. 20th Design Automat. Conf., June 1983.

....match the voltage of output and input signals of two interacting partitions. Discussion of the above problems is beyond the scope of this paper. B. The Effect of Clock Partitioning The relation between clock partitioning and power and delay is shown in Fig. 10 for a typical example, i.e. FACET [31]. The solid line curves in Fig. 10 show the power and partitioning tradeoff. The lower bound for power consumption of such circuit (Pmin ) can be estimated (even before synthesis) as the summation of power dissipation of all ALU s required based on DFG. As the curves show as a general trend, the ....

....VDD Vmax ) as we discussed before. The curves are almost parallel since we use the same derating factor based on Fig. 9(b) For simplicity, we combined these two curves together to have the effect of VDD on both factors power and delay simultaneously. Fig. 10 shows the curves for the FACET [31] example for one, two, three and four clock partitions. Note that the power and delay readings should be done using left and right vertical axes, respectively. C. Power Voltage Delay Tradeoff Method Briefly speaking, we obtain the allocator results of the same schedule using different number of ....

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C. Tseng and D. P. Siewiorek, "FACET: A Procedure for the Automated Synthesis of Digital Systems," in Proc. 20th design Automation Conf., June 1983, pp. 566-572.

.... (LSSD) 21] and 2) different registers in a testable design, such as Built In Self Testing (BIST) Depending on the test methodology, there are different type of test registers, such as: BILBO, TPGR and MISR [21] As an example, we selected the datapath of the FACET example (introduced first in [22]) presented in [23] The schedule and datapath are shown in Fig. 5(a) and (b) respectively. Note that the data for division come from R5 and R7. Consider two design styles: In the first, registers R1; R3; R4; R5 are master slave and R2; R6; R7 are normal. In the second style, we have a testable ....

....our synthesis tool, SYNTEST [17] Note that the datapaths in the two tables are produced with different set of options and are not structurally equivalent. We used our own layout estimator at the RT level to estimate the wire lengths between the components [18] The examples are HAL [19] FACET [22] and four digital filters including the fifth order elliptical filter chosen as a benchmark for the 1988 High Level Synthesis Workshop. They have been widely used in the literature as benchmarks. The CPU time for running the delay estimator is less than four seconds for these examples. The wall ....

C. Tseng and D. Siewiorek, "FACET: A Procedure for the Automated Synthesis of Digital Systems," in Proc. 20th DAC, June 1983.

....to a register module whose bit width is the maximum of the bit widths of all carriers in the group. Various register optimization strategies have been proposed [18] Our register optimization algorithm is based on a clique partitioning heuristic on the lines proposed by Tseng and Siewiorek [19]. Figure 3.6 shows the dfg following register optimization and binding. Interconnect Optimization The goal of interconnect optimization is to assign an interconnect path to each value transfer in the dfg. Interconnect paths are formed using 1. Generate a set of valid module bags. 2. for each ....

C. Tseng and D. P. Siewiorek, "Facet : A Procedure for the Automated Synthesis of Digital Systems," 20th ACM/IEEEDesign Automation Conference, pp. 490-496, 1983.

....determines the hardware cost speed trade offs of a design. There are several scheduling methods in HLS. The simplest scheduling technique is As Soon As Possible (ASAP) scheduling where the operation in data flow graph (DFG) are scheduled into control steps from the first to the last. FACET [1] and MIMOLA [2] systems use this technique to find near optimal solution. One commonly used approach is list scheduling. It has been adapted in many systems such as [3] and [9] In this scheme, ready operations are kept in an ordered list based on a local priority function and are scheduled in ....

C. Tseng and D. Siewiorek, "FACET: A Procedure for the Automated Synthesis of Digital Systems," in Proc. 20th design Automat. Conf., June 1983.

....reports on five different designs of the same example: conventional allocation using non gated single clock, conventional allocation using gated single clock, commonly used in industries [10] and three datapaths based on latch implementation . In Table 1 we show our results for the FACET example[14]. As expected, there is a reduction of power as the number of clocks increases, from 6.92 mW (for the conventional gated clocks) to 3.52 mW (for 3 clock method) which is 49 . Also, notice that for our scheme with one clock the power has increased as compared to the Conventional with Gated Clocks. ....

C. Tseng and D. P. Siewiorek, "FACET: A Procedure for the Automated Synthesis of Digital Systems," in Proc. 20th design Automation Conf., June 1983, pp. 566-572.

....GCD 4 16 9 2901 23 748 216 Table 1: Number of times BRANCH ON BIND( executed on experimental examples. 5 Results Table 2 shows results comparing our approach against an approach assuming a direct mapping of HDL operators to RT units. Facet is a modified version of an example description from [TsSi83], a carry input was added for the additions in the description. FPA is a model of a IEEE standard 32 bit floating point adder subtractor [HLSWB] GCD is a description of an 8 bit greatest common divisor circuit [HLSWB] The AM2901 is a model of a 4 bit ALU [HLSWB] Each approach allocated units to ....

C. Tseng and D. Siewiorek "Facet: A Procedure for Automated Synthesis of Digital Systems" Proceedings of the Design Automation Conference (DAC), pp. 490--496, 1983. A Pertinent VHDL portions of examples A.1 Facet+ entity FACET is port (V6,V4,V10,V1, V2: in BITVECTOR(3 downto 0);

....over their entire scope of visibility and relative to all the other carriers in the entire specification. This approach is quite expensive in computer time and memory, as it involves determining the maximal compatibility classes among a large number of carriers, a process known to be NP complete [2, 19]. On the other hand, the proposed algorithm achieves nearly the same effect of global optimization without using explicit inline expansion. The compatibility between all possible pairs of carriers in the entire specification is not evaluated and hence gain in both memory and time. Experimental ....

....register optimization is viewed as the problem of mapping carriers onto registers. Lifetime analysis of carriers is performed to establish compatibility relation between pairs of carriers. The problem of finding a minimal set of registers is then modeled as a clique partitioning problem. FACET [2], HAL [10] and CHARM [11] use carrier based techniques for register optimization. Some synthesis researchers, most notably De Micheli, 1] suggested modeling behavioral specifications as hierarchical graphs. In such a representation one can conveniently model loop bodies as modules in the ....

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C. Tseng and D. P. Siewiorek, "Facet : A Procedure for the Automated Synthesis of Digital Systems," 20th ACM/IEEEDesign Automation Conference, pp. 490-496, 1983.

....Critical Specification Variables Critical RTL Registers var 1 var 2 var m reg 1 reg 2 reg m Figure 3. Register Allocation with No Optimization 5.2 Carrier Based Register Allocation The carrier based register allocation scheme yields a mapping from the variables to the registers. FACET [16], HAL [17] and CHARM [18] use carrier based techniques for register optimization. Register optimization is only possible when two (or more) variables, have non overlapping lifetimes, in which case they are bound to the same register. Therefore the mapping from the specification variables to RTL ....

C.Tseng, D.P. Siewiorek, "Facet: A Procedure for the Automated Synthesis of Digital Systems", 20th ACM/IEEE Design Automation Conference, pp. 490-496, 1983.

....to a register module whose bit width is the maximum of the bit widths of all carriers in the group. Various register optimization strategies have been proposed [30] Our register optimization algorithm is based on a clique partitioning heuristic on the lines proposed by Tseng and Siewiorek [31]. Figure 9 shows the dfg following register optimization and binding. 13 a b C 0 1 2 3 ALU2 ALU1 ALU1 T F ALU1 ALU2 , 4 bit 4 bit Figure 8: Scheduled and Operator Bound DFG and Partial Data Path 14 a b C 0 1 2 3 Z t1 t2 T F ALU2 ALU1 ALU1 4 bit ....

C. Tseng and D. P. Siewiorek, "Facet : A Procedure for the Automated Synthesis of Digital Systems," 20th ACM/IEEEDesign Automation Conference, pp. 490-496, 1983.

....resource k. Various subtasks of architectural synthesis have been identified; e.g. scheduling, allocation of hardware resources, and the assignment of operations to hardware resources [GDWL92] Various algorithms and models have been proposed for these subtasks. For example, clique partitioning [ST83], bipartite graph matching [Tim95b] simulated annealing[DN89] integer programming [GE91, Geb92] and many heuristics have been proposed. 3.2 IP based Synthesis Among those approaches just mentioned, IP based models exhibit a number of interesting features, including ffl the existence of a formal ....

D.P. Siewiorek and C.J. Tseng. Facet: A procedure for the automated synthesis of digital systems. 20th Design Automation Conf., pages 490--496, 1983.

....represent the number of technology independent, equivalent 2 input logic gates to implement the allocated units. Table 1 shows results comparing our approach against an approach assuming a direct mapping of HDL operators to RT units. Facet is a modified version of an example description from [14], a carry input was added for the additions in the description. FPA is a model of a IEEE standard 32 bit floating point adder subtractor [5] GCD is a description of an 8 bit greatest common divisor circuit [5] The AM2901 is a model of a 4 bit ALU [5] Each approach allocated units to an ....

C. Tseng and D. Siewiorek "Facet: A Procedure for Automated Synthesis of Digital Systems" Proceedings of DAC , pp. 490--496, 1983.

....8 concludes this report with a summary and future research topics. 6 CHAPTER 1. INTRODUCTION Chapter 2 Related work Almost all early approaches to high level synthesis partitioned the problem into subproblems for scheduling, allocation and binding. This includes the work by Tseng and Siewiorek [ST83], Marwedel [Mar86] and others (see [MPC90] for a survey) This work helped finding solution methods for these subproblems. Later it was recognized, that these subproblems should be solved simultaneously in order to avoid suboptimal results. The work of Gebotys is especially stimulating in this ....

D.P. Siewiorek and C.J. Tseng. Facet: A procedure for the automated synthesis of digital systems. 20th Design Automation Conf., pages 490--496, 1983.

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C. Tseng and D. P. Siewiorek. FACET: A procedure for automated synthesis of digital systems. In Proc. of the 20th Design Automation Conference, pages 566--572, June 1983.

No context found.

C. Tseng and D. P. Siewiorek. FACET: A procedure for automated synthesis of digital systems. In Proc. of the 20th Design Automation Conference, pages 566--572, June 1983.

No context found.

C. Tseng and D. P. Siewiorek. FACET: A procedure for automated synthesis of digital systems. In Proc. of the 20th Design Automation Conference, pages 566--572, June 1983.

No context found.

C.J. Tseng and D.P. Siewiorek. Facet: A Procedure for the Automated Synthesis of Digital Systems. In Proc. of the 20th DAC, pp. 490-496. ACM/IEEE, Miami, FL, June, 1983.

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