E. Brewer, C. Dellarocas, A. Colbrook, and W. Weihl, "Proteus: a high performance parallel architecture simulator," Laboratory for Computer Science, MIT, Boston, MA, Technical Report MIT/LCS/TR-516, September 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....expense of purchasing it; second, one can do the simulation fast there is no need to simulate the workstation s behavior (for example down to the level of memory references) since that part of the hardware is readily available. Many of the early simulators were designed for sequential execution [9, 13, 14]. However, even with the use of abstract models and direct execution, sequential program simulators tended to be slow with slowdown factors ranging from 2 to 35 for each process in the simulated program [9] Several recent efforts have been exploring the use of parallel execution [10, 17, 18, 24, ....

....available. Many of the early simulators were designed for sequential execution [9, 13, 14] However, even with the use of abstract models and direct execution, sequential program simulators tended to be slow with slowdown factors ranging from 2 to 35 for each process in the simulated program [9]. Several recent efforts have been exploring the use of parallel execution [10, 17, 18, 24, 25, 28, 29] to reduce the model execution times, with varying degrees of success. In order to have multiple simulation processes and maintain accuracy, simulations use protocols to synchronize the ....

E. A. Brewer, A. Colbrook, C. N. Dellarocas, and W. E. Weihl. PROTEUS: a high-performance parallelarchitecture simulator. In Proceedings of 1992 ACM Sigmetrics and Performance, Newport, RI, 1992.

....quite simple and does not enable the modeling of various caches. Bhuyan et al. 2] use simulation to study the impact of CC NUMA memory management policies in combination with interconnection network switch designs on application performance. The simulation environment is built on top of PROTEUS[3], an execution driven simulator for shared memory machines. In order to evaluate memory and network, PROTEUS was extended with various data distribution schemes and network switches. In comparison with these systems, SIMT is more flexible in terms of memory hierarchy simulation. The cache ....

E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl. PROTEUS: A High-performance Parallel-Architecture Simulator. Technical Report MIT/LCS/TR-516, Massachusetts Institute of Technology, September 1991.

....of non linearizable operations. Finally, in Section 5 we provide empirical measurements of the extent to which timing can affect linearizability in Bitonic networks and Diffracting trees. These results were collected on a simulated Alewife [1] shared memory multiprocessor using the Proteus [8] simulator. We use our c c2 measure to mathematically support our experimental results: that in a variety of normal situations, the Bitonic counting networks of Aspnes et al. 4] exhibit linearizable behavior. In fact, for high concurrency levels, our results show that even if one skews system ....

....Management Unit on each node holds the cache tags and implements the memory coherence protocol by synthesizing messages to other nodes. Our experiments make use of the shared memory interface only. To simulate the Alewife we used Proteus, 3 a multiprocessor simulator developed by Brewer et al. [8]. Proteus simulates parallel code by multiplexing several parallel threads on a single CPU. Each thread runs on its own virtual CPU with accompanying local memory, cache and communications hardware, keeping track of how much time is spent using each component. In order to facilitate fast ....

E.A. Brewer, C.N. Dellarocas, A. Colbrook, W.E. Weihl, Proteus: a high-performance parallelarchitecture simulator, Technical Report MIT/LCS/TR-516, M1T Laboratory for Computer Science, September 1991.

....latencies observed for different network architectures. Section 5 presents the execution times of each application for different network architecture. Finally, section 6 presents the conclusion and the direction for further work in this area. 2 Simulation Model Our simulator is based on Proteus [12]. However, the simulator implemented MIN using an analytical model presented in [13] We have modified the simulator extensively to exactly model MINs with packet switching and wormhole routing. For wormhole routing, we have also incorporated virtual channels and multi flit buffers. The system ....

E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl, "Proteus: A HighPerformance Parallel-Architecture Simulator," Technical Report MIT/LCS/TR-516, Massachusetts Institute of Technology, September 1991.

....Section 4 presents and discusses the results of our simulations. Section 5 provides the details about the execution of each application. Finally, section 6 presents the conclusion and the direction for further work in this area. 2 Simulator Development We have modified the Proteus simulator [14] extensively to incorporate virtual channels, multi flit buffers, multiple internal links and other architectural features. The system considered for evaluation in this paper is a cache coherent shared memory multiprocessor connected through a two dimensional torus network. The network is wormhole ....

E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl, "Proteus: A HighPerformance Parallel-Architecture Simulator," Technical Report MIT/LCS/TR-516, Massachusetts Institute of Technology, September 1991.

....and runtime system, which then is responsible for the details of data structure layout and task decomposition. At the time that I conducted the experiments, an initial version of Prelude had been designed and mostly implemented on top of Proteus, a highperformance simulator for MIMD architectures [6, 7]. Proteus executes programs written in a superset of C that has special facilities for handling shared memory accesses, thread management, message passing, and synchronization. When the Prelude implementation is complete, Proteus will also be able to execute Prelude programs. Proteus provides a ....

E.A. Brewer, C.N. Dellarocas, A. Colbrook, and W.E. Weihl. Proteus: A high-performance parallel-architecture simulator. Technical Report MIT/LCS/TR-516, MIT Laboratory for Computer Science, September 1991.

....originate on the processor where the original, or master , copy of a node was created. Other copies are updated by sending the complete new version of the node after every change. System Setup We implemented a distributed B tree using Proteus, a high performance MIMD multiprocessor simulator [BDCW91, Del91] Proteus provided us with a basic multiprocessor architecture independent processors, each with local memory, that communicate with messages. It also provided exceptionally valuable tools for monitoring and measuring program behavior. On top of Proteus we created a simple structure for ....

E. Brewer, C. Dellarocas, A. Colbrook, and W. E. Weihl. Proteus: a Highperformance Parallel Architecture Simulator. Technical Report TR-516, MIT, 1991.

....expense of purchasing it; second, one can do the simulation fast there is no need to simulate the workstation s behavior (for example down to the level of memory references) since that part of the hardware is readily available. Many of the early simulators were designed for sequential execution [9, 13, 14]. However, even with the use of abstract models and direct execution, sequential program simulators tended to be slow with slowdown factors ranging from 2 to 35 for each process in the simulated program [9] Several recent efforts have been exploring the use of parallel execution [10, 17, 18, 24, ....

....available. Many of the early simulators were designed for sequential execution [9, 13, 14] However, even with the use of abstract models and direct execution, sequential program simulators tended to be slow with slowdown factors ranging from 2 to 35 for each process in the simulated program [9]. Several recent efforts have been exploring the use of parallel execution [10, 17, 18, 24, 25, 28, 29] to reduce the model execution times, with varying degrees of success. In order to have multiple simulation processes and maintain accuracy, simulations use protocols to synchronize the ....

E. A. Brewer, A. Colbrook, C. N. Dellarocas, and W. E. Weihl. PROTEUS: a high-performance parallelarchitecture simulator. In Proceedings of

....side, there are two main disadvantages: simulators can be slow and require small data sets. Although traditional simulators of parallel architectures are too slow to run real applications [11] 12] new simulation environments as Tangolite [15] the Rice Parallel Processing Testbed [6] Proteus [3] and the Trace Factory [23] are very fast [5] The amount of main memory on a workstation is indeed a serious limiting factor. This space problem can also become a performance problem when the address space overflows in the swap space. As a consequence, simulators typically promote small data ....

E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl. PROTEUS: A High-Performance Parallel-Architecture Simulator. Technical Report MIT/LCS/TR-516, MIT, September 1991.

....to analyze multiprocessor systems. For instance, Limes [17] simulates N processors running a parallel application. The tool implements the assembly language level, and can be used to evaluate architectures or parallel algorithms. PROTEUS is a high performance simulator for MIMD multiprocessors [18]. It was developed to simulate a wide range of architectures, trying to improve accuracy and performance. Several processors are connected via a bus or a network, but it is devoted to execute an application in multiple CPUs. In [19] a tool for the modeling and simulation of clustered computers was ....

BREWER, E.A., DELLAROCAS, C.N., COLBROOK, A. AND WEIHL, W.E. "PROTEUS: A High-Performance Parallel-Architecture Simulator". Technical Report TR-516, MIT / LCS, Laboratory for Computer Science, Cambridge, MA, September 1991.

....tool is a better solution. The right first time approach of VLSI design (and Total Quality Management) should be extended to cover parallel software. Some simulation tools employ direct execution to evaluate performance of parallel programs on parallel architectures (e.g. MIT Proteus [11], Stan ford Tango [12] WWT [13] This is an excellent approach for obtaining fast, realistic simulations if the processor you re running the simulation on is very similar to the processor used in the parallel machine but we believe that this assumption is sometimes too restrictive and a ....

E.A. Brewer, C.N. Dellarocas, A.Colbrook, W.E.Weihl "PROTEUS: A High Performance Parallel-Architecture Simulator", Technical Report MIT/LCS/TR-516, MIT Laboratory for Computer Science, September 1991

....pipeline system that used a pipeline length proportional to the length of the key. We first implemented a (2 B , 2 ) search tree using a top down node splitting scheme. We then implemented the search tree using the bottom up algorithm. Both of these algorithms have been implemented using Proteus [De191, Bre91, BDCW91], a multiprocessor simulator developed at MIT. We measured the throughput and response times for various processor array lengths, tree branching factors, query mixes, message passing paradigms and one way message delays. From these measurements we compared the performance of the algorithms and ....

E.A. Brewer, C.N. Dellarocas, A. Colbrook, and W.E. Weihl. PROTEUS: A high- performance parallel-architecture simulator. Technical Report MIT/LCS/TR-516, MIT Lab- oratory for Computer Science, 1991.

....the CM 5 is a time shared and space shared multi user machine. All of my experiments on the CM 5 are run in dedicated mode, so the e ect of sharing the machine does not show up in my measurements. 4. 4 Proteus and Simulated Alewife Our initial research was performed on the Proteus simulator [15], an execution driven parallel architecture simulator. Proteus delivers high performance by directly executing instructions rather than simulating them; simulator timing code is inserted into assembly code. As a result, the simulated processor architecture is the same as that of the architecture ....

E.A. Brewer, C.N. Dellarocas, A. Colbrook, and W.E. Weihl. "Proteus: A High-Performance Parallel Architecture Simulator". Technical Report MIT/LCS/TR-516, MIT Laboratory for Computer Science, September 1991.

....forwarded from the old tail. 5 Support for Prototyping Critical to the success of PRELUDE as a vehicle for studying languages and runtime systems is the ability to experiment on a wide variety of MIMD architectures. To facilitate such experiments we have built a retaxgetable simulator, PROTEUS [De191, Bre91, BDCW91], that simulates MIMD architectures and provides support for sophisticated data collection and display. PROTEUS simulates MIMD multiprocessors in which independent processor nodes are connected via an interconnection medium. The interconnection medium can be either a bus, a direct network such as ....

E.A. Brewer, C.N. Dellarocas, A. Colbrook, and W.E. Weihl. PROTEUS: A high- performance parallel-architecture simulator. Technical Report MIT/LCS/TR-516, MIT Lab- oratory for Computer Science, 1991.

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E. Brewer, C. Dellarocas, A. Colbrook, and W. Weihl, "Proteus: a high performance parallel architecture simulator," Laboratory for Computer Science, MIT, Boston, MA, Technical Report MIT/LCS/TR-516, September 1991.

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E. A. Brewer, C. Dellarocas, A. Colbrook, and W. E. Weihl. PROTEUS: A High-Performance Parallel-Architecture Simulator. Measurement and Modeling of Computer System, pages 247--8, 1992.

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E.A. Brewer, C.N. Dellarocas, A. Colbrook and W.E. Weihl. Proteus: A High-Performance Parallel-Architecture Simulator. MIT Technical Report /MIT/LCS/TR-561, September 1991.

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E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl. Proteus: A High-Performance Parallel-Architecture Simulator. Technical Report MIT/LCS/TR-516, Massachusetts Institute of Technology, September 1991. 15

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Brewer E. A., Dellarocas C. N., Colbrook A., Weihl W. E.: Proteus: A High-Performance Parallel-Architecture Simulator. Technical Report MIT/LCS/TR-516, Massachusetts Institute of Technology, Cambridge 1991.

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Brewer, E.A., Dellarocas, C.N., Colbrook, A., Weihl, W.E.: Proteus: A highperformance parallel-architecture simulator. In Proc. 1992 ACM Sigmetrics and Performance '92 Conference, (1992) 247--248

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E. A. Brewer et al. PROTEUS: A High-Performance Parallel-Architecture Simulator. Technical Report MIT/LCS/TR-516, MIT Laboratory for Computer Science, September 1991.

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E. A. Brewer, C. Dellarocas, A. Colbrook, and W. E. Weihl. PROTEUS: A High-Performance Parallel-Architecture Simulator. Measurement and Modeling of Computer System, pages 247--8, 1992.

No context found.

E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl. PROTEUS: A High-performance Parallel-Architecture Simulator. Technical Report MIT/LCS/TR-516, Massachusetts Institute of Technology, September 1991.

No context found.

E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl. Proteus: A highperformance parallel-architecture simulator. Technical Report MIT/LCS/TR-516, Massachusetts Institute of Technology, September 1991.

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E.A. Brewer et al., Proteus: A High Performance Parallel Architecture Simulator, Tech. Report MIT/LCS/ TR516, Massachusetts Institute of Technology, Cambridge, Mass., 1991.

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