G. Lauterbach, "Accelerating Architectural Simulation by Parallel Execution of Trace Samples," In Hawaii International Conference on System Sciences, Volume 1: Architecture, January 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....be used as well for selecting reduced input data sets. A reference input set and a resembling reduced input set will be situated close to each other in the dimensional space built up by the principal components. Another important research topic that is related to this paper is trace sampling [5, 6, 13, 16]. In trace sampling, several samples are taken from a program execution so that the total number of instructions in the samples is significantly less than the total number of instructions of a complete execution. In order to make viable design decisions based on these sampled traces, a sampled ....

G. Lauterbach. Accelerating architectural simulation by parallel execution of trace samples. Technical Report SMLI TR-93-22, Sun Microsystems Laboratories Inc., Dec. 1993.

....more complex and may induce slowdowns in the 1,000 10,000 range. Such a simulation rate does not allow to consider realistic simulation of the entire workload of a desktop computer or even a large application executing trillions of instructions. Simulating such applications requires sampling [6]. Therefore, apart very specific studies like cache behavior analysis of the whole SPEC92 benchmark suite [3] which used months of CPU time, most studies on cache or micro architecture are performed using the first 100,000,000 or billion instructions of an application (maybe the first 50,000,000 ....

....by the simulator [10] 2. 2 Principles of Code Cloning Tracing For large applications consuming several CPU hours, the trace cannot be realistically stored or consumed at execution time (trillions of trace elements ) Techniques to reduce this large data set include trace sampling as suggested by [4, 6, 8]. However, such techniques also slow the overall trace collection process. Instead of sampling the resulting trace after (or during) execution to reduce the trace volume 2 , we propose to sample the execution of the program by implementing two execution modes: a no trace collection mode and a ....

G. Lauterbach. Accelerating architectural simulation by parallel execution of trace samples. In Trevor N. Mudge and Bruce D. Shriver, editors, Proceedings of the 27th Hawaii International Conference on System Sciences. Volume 1 : Architecture, pages 205--210, Los Alamitos, CA, USA, January 1994. IEEE Computer Society Press.

....the worth (and risk) of using trace sampling methods in conjunction with the basic parallel trace processing paradigm. Prior attempts in reducing architectural simulation cost have been largely limited to trace size compaction methods. The size of the trace can be reduced through sampling (e.g. [1 5]) or synthetic regeneration [6] In [1] parallel processing on a cluster of workstations was applied to collected trace samples. However, the process of collecting trace samples was reported to be time consuming and the accuracy of workload metrics (e.g. basic block frequencies) was stated to be ....

....methods in conjunction with the basic parallel trace processing paradigm. Prior attempts in reducing architectural simulation cost have been largely limited to trace size compaction methods. The size of the trace can be reduced through sampling (e.g. 1 5] or synthetic regeneration [6] In [1], parallel processing on a cluster of workstations was applied to collected trace samples. However, the process of collecting trace samples was reported to be time consuming and the accuracy of workload metrics (e.g. basic block frequencies) was stated to be low. Also, warm start correction for ....

G. Lauterbach, "Accelerating architectural simulation by parallel execution of trace samples," Proc. 27th Ann. Hawaii Int'l. Conf. on System Sciences, pp. 205--210, 1994.

....an exhaustive search of the design space using these workloads is time consuming and expensive. Statistical sampling [8] 12] has been used successfully to alleviate these problems in cache simulations and, in recent years, it has also been extended to the simulation of processors [2] 10] [9]. In general, statistical techniques used in experiments reduce a large data set into a smaller representative set. The results obtained from the sampling must be representative of the entire workload to be accurate. The representativeness, therefore, depends on the method of sample collection. ....

.... performance modeling technique for the PowerPC 603 microprocessor that employed the use of a sample of one million instructions equally divided into 200 clusters [10] At the same time, Lauterbach proposed an iterative sampling verification resampling technique for processor performance simulation [9]. This sampling method extracted 100 clusters at random intervals with each cluster consisting of 100; 000 instructions. These selected clusters are checked against the full trace to monitor the sample s representativeness of the instruction frequencies, basic block densities, and cache ....

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G. Lauterbach. Accelerating architectural simulation by parallel execution. In Proc. 27th Hawaii Int'l. Conf. on System Sciences, Maui, HI, Jan. 1994.

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G. Lauterbach, "Accelerating Architectural Simulation by Parallel Execution of Trace Samples," In Hawaii International Conference on System Sciences, Volume 1: Architecture, January 1994.

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G. Lauterbach, "Accelerating Architectural Simulation by Parallel Execution of Trace Samples," In Hawaii International Conference on System Sciences, Volume 1: Architecture, January 1994.

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G. Lauterbach. Accelerating architectural simulation by parallel execution of trace samples. Technical Report SMLI TR-93-22, Sun Microsystems Laboratories, December 1993.

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