P. Landman, Low power architectural design methodologies, Ph.D Dissertation, U.C. Berkeley, Aug 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....In some cases, activity inside a functional unit can depend more on one input than another and can also depend on relationships between the inputs. Landman suggested a method for estimating power inside functional units having bit sliced or bit meshed structures based on activity of input nodes [10]. This method can be used to characterize the effect input node activity has on power dissipation inside a functional unit. By reducing activity at particular inputs according to this type of information, power can be significantly reduced inside the functional unit. 12 Glitching on inputs to ....

....and addressing special cases [9] 12] There are only a couple models that practically relate data characteristics to transition activity. Others, discussed in [17] 18] are limited by difficulty of use or constraining assumptions. One practical model is the Dual Bit Type (DBT) model [10], 11] which uses probabilistic parameters to characterize the data related activity. This model was developed to determine ranges for two types of activity that could be used to estimate power dissipation inside certain functional units. While the utility of this model has been successfully ....

[Article contains additional citation context not shown here]

P. Landman, Low-Power Architectural Design Methodologies, Ph.D. Dissertation, UC Berkeley, August 1994.

.... While the relationship between switching activity at inputs of a functional unit or memory unit and switching activity of nodes inside the unit is not as easily understood, there are methods for estimating power inside units having specific structures based on activity of input output nodes [7], 8] Power can be significantly reduced inside a functional or memory unit by reducing activity at particular inputs according to this type of characterization. However, it is not enough to be able to estimate the effect activity of a particular design choice has on power consumption. This is ....

....special cases [12] 16] There are only a couple models that practically relate data characteristics to transition activity in general. Others, discussed in [17] 19] are limited by difficulty of use or constraining assumptions. One of the more practical models is the dual bit type (DBT) model [7], 14] which uses probabilistic parameters to characterize the data related activity. This model was developed to determine ranges for two types of activity that can be used to estimate power consumption inside certain functional units. The main benefit of the DBT model is its ability to ....

[Article contains additional citation context not shown here]

P. Landman, "Low-power architectural design methodologies," Ph.D. dissertation, Univ. California, Berkeley, CA, Aug. 1994.

.... cost of an on chip memory transfer is approximated by the power cost of the memory access itself, since the power consumed upon on chip busses is much smaller than the internal power consumption of on chip memories The power consumed on onchip memory accesses is estimated using Landman s model [8]. According to this, the power consumed on memory accesses is a function of the memory size, the access frequency, the technology, the number and the type (R or R W) of ports and the number of bits of the accessed word. In this paper all memories are assumed to have a single read write port. It is ....

....is given as: # , DD ACCESS ACCESS CHIP ON V Words length Word F f P P = 2) For a given supply voltage the function F of equation (2) determines the relation between the memory power consumption and the memory size and depends only on technology. Such a function is described in [8] and is used here for the estimation of memory access power cost. The bus driver, the chips I O pins (bonding wires and pads) the bus wires and the memory banks consume power during an off chip memory access. High level accurate estimation of the effective capacitance corresponding to each one ....

P. Landman, Low power architectural design methodologies, Doctoral Dissertation, U.C. Berkeley, Aug. 1994.

....is much smaller than the internal power consumption of on chip memories, thus the energy cost of an on chip memory transfer is approximated by the energy cost of the memory access itself. The energy consumed on accesses to the on chip memories is estimated using the model presented by Landman in [9], 10] According to this model the energy dissipated on memory accesses is a function of the memory size in terms of stored words, the number of bits per stored word, the number of access, the technology and the number and the type (R or R W) of ports. It is assumed that the energy is linearly ....

....memory accesses is given as: E## #### # N Accesses ## #### # f #N words;N bits; N ports# : 10) For a given supply voltage the function f of Eq. 10 determines the relation between the memory energy consumption and the memory size and depends only on technology. Such a function is described in [9], 10] 8] and is used for the estimation of memory access energy cost in this paper. During an off chip memory access, power is consumed by the bus driver, the memory and processing element(s) chip I O pins (bonding wires and pads) the bus wires and the memory banks. High level accurate 5 ....

P. Landman, Low power architectural design methodologies, Ph.D. thesis, U. C. Berkeley, Aug. 1994.

....on technology and the specific vendor used. Thus the power consumed by an on chip memory is given by the following equation: 1 ( # size f accesses E = The function f that has been used to produce the energy figures that will be presented in the rest of the paper is described in [2]. For the estimation of the energy consumption of the off chip memories the low power 1 Mb SRAM presented in [3] is assumed as in [4] since no other figures for power consumption of off chip memories are currently available by the vendors. This assumption leads to an energy dissipation of 2.6 ....

P. Landman, "Low power architectural design methodologies", Doctoral Dissertation, U. C. Berkeley, Aug. 1994.

....i (instr word length, code size, f) 2) where c is a member of the copy tree (CT) 6] P r ( Pw ( and P i ( is the power consumption estimate for read operation, write operation, and instruction fetch, respectively. For memory power consumption estimation we use the models reported in [2]and [8]. The total delay cost function is obtained by: Delay cost = max i=1, N #cycles processor i (3) where #cycles processor i denotes the number of the executed cycles of the i th processor (i = 1, 2, N) Also, the maximum number of cycles is the performance of the system. In order ....

P. Landman, Low power architectural design methodologies, Doctoral Dissertation, U.C. Berkeley, Aug. 1994.

....for most modern memory [15] So the power consumption due to memory accesses is given as: S F f P ACCESS ACCESS = 8) The function F of equation (8) determines the relation between the memory power consumption and the memory size and depends only on technology. Such a function is described in [9] and is used for the estimation of memory access power cost in this paper. 4. PROPOSED RESEARCH The aim of our methodology is the minimization of the power consumption of multimedia applications realized on processorcores with application specific data memory organization, while meeting ....

P. Landman, Low power architectural design methodologies, Doctoral Dissertation, U.C. Berkeley, Aug. 1994.

....function f used for the results that will be presented in this paper is proprietary and for this reason no details can be given and only relative power figures will be presented in the rest of the paper. In principle it is less linear with respect to memory size than the one proposed by Landman in [21]. For the estimation of the power consumption of the offchip memories the low power 1 Mb SRAM presented in [22] is assumed, similar to [20] since no parameterized models relating the power consumption of an off chip memory to its parameters (e.g. size, word length etc. are known to exist. The ....

P. Landman, "Low power architectural design methodologies", Doctoral Dissertation, U.C. Berkeley, Aug. 1994.

.... A first order approximation of the dynamic energy consumption of CMOS circuitry is given by the formula: P d = C eff V f(3) where P d is the power in Watts, C eff is the effective switch capacitance in Farads, V is the supply voltage in Volts, and f is the frequency of operations in Hertz [33]. The power dissipation arises from the charging and discharging of the circuit node capacitance found on the output of every logic gate. Every low to high logic transition in a digital circuit incurs a voltage change #V, drawing energy from the power supply. C eff combines two factors C, the ....

....tools, that provide accurate and reliable results at various levels of abstraction. Power analysis tools are available primarily at the gate and circuit levels, and not at the architecture and algorithm levels where they could really make an impact. Current research is trying to fill this gap [33][43] 86] 2.2.4 How much is a picojoule In Table 3 we compare the energy of a transition of a CMOS gate (about 1 picojoule) with a variety of energy quantities. Note that neural transitions are an order of magnitude more efficient (in average) An assignment consumes about 100 picojoules for a ....

[Article contains additional citation context not shown here]

Landman P.E.: "Low-power architectural design methodologies", Ph.D. thesis, University of California at Berkeley, 1994.

....portability, reliability and the today s high demand of mobile devices ask for new evaluation methods and techniques to attack this problem. The current prevision show that the energy battery will not increase drastically in the near future due to actual technology problems and for safety reasons [2]. On the other hand, portable devices of the next generations will include several multimedia functionalities and will be able to sustain high performance through powerful system architecture [3] The historical trend in the design of computer architectures was based on performance with minor ....

Paul Landman. Low Power Architectural Design Methodologies. PhD thesis, University of California at Berkeley, 1994.

....transfer is one order of magnitude higher in both hardware and software (Wuytack, 1998) 3.1 Memory power consumption Cx0 [fF] Cx1 [fF] Cx2 [fF] Cx3 [fF] C read 9707 108 1126 6 C write 7994 117 759 9 Table 1. Empiricially determined capacitive constants for the black box capacitance model of (Landman, 1994), see also (Wuytack, 1998) Landman (1994) presented a black box capacitance model for an on chip SRAM which demonstrates clearly the dependency of the memory power consumption on both the memory size and the access rate: Let W be the word depth, N the bit width, and WN the number of storage ....

....both hardware and software (Wuytack, 1998) 3.1 Memory power consumption Cx0 [fF] Cx1 [fF] Cx2 [fF] Cx3 [fF] C read 9707 108 1126 6 C write 7994 117 759 9 Table 1. Empiricially determined capacitive constants for the black box capacitance model of (Landman, 1994) see also (Wuytack, 1998) Landman (1994) presented a black box capacitance model for an on chip SRAM which demonstrates clearly the dependency of the memory power consumption on both the memory size and the access rate: Let W be the word depth, N the bit width, and WN the number of storage cells. Then, C read = C read0 C read1 W C ....

Landman, P., Low-Power Architectural Design Methodologies, Ph.D. thesis, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA, 1994.

.... are implemented (resource selection) On behavioral level, the power consumption of di erent implementation alternatives can be estimated as a function of the input switching activity either using a parametric analytical model or a look up table based model (Landman and Rabaey, 1993, 1994; Landman, 1994). Such models can be used to guide resource selection in choosing modules that optimally trade o area vs. performance vs. power to implement a given operation. Other ecient techniques for behavioral power optimization include the choice of number representation and bus encoding. These determine ....

Landman, P. E., Low-Power Architectural Design Methodologies, Ph.D. thesis, College of Engineering, University of California, Berkeley, 1994.

....the fact that the exact circuit structure is not yet fixed. In this paper activity is estimated by calculating Hamming distance at the output nodes of basic operations (e.g. addition, multiplication etc) during functional simulation. For the effective capacitance estimation the models presented in [10] some of which are also available on the web [11] are used. Even though the accuracy of this method is poor, the claim is that it suffices for the purpose of comparing alternative power management scenaria at the behavioral level. However, any other, behavioral level power estimation method can be ....

....this behavioral cluster to the same resource then the power management for this resource is disabled. A behavioral synthesis algorithm that targets functional pipelined architectures and that takes into account the power management decisions made by the proposed methodology has been developed [10]. Analysis of this algorithm is out of the scope of this paper. 4. PROPOSED METHODOLOGY APPLIED IN A DECT RECEIVER For the implementation of a DECT receiver the behavior described by the block diagram of fig. 1 and the simplified CDFG of fig. 2 is considered. The behavior of the receiver is as ....

P. Landman, "Low power architectural design methodologies", Ph.D. Dissertation, U.C. Berkeley, Aug. 1994.

....converges to the average power. The convergence is tested by statistical mean estimation techniques. 2.2 Architectural Level of Abstraction At the architectural level, Landman et al. [41] presented a technique for the characterization of module library using signal statistics. Landman et al. [66] presented a methodology for low power design space exploration at the architectural level of abstraction. Black box power models for the architectural level components were generated [67] and used to estimate power while preserving the accuracy of the gate or circuit level estimation. Powell et ....

P. Landman, "Low-Power Architectural Design Methodologies", Ph.d Thesis, Memorandum No. UCB/ERL M94/62, 30th August 1994.

....and architectural parameters. Chandrakasan et al. 6, 7] described a high level synthesis system, HYPER LP, which uses a variety of architectural and computational transformations to minimize power consumption in applicationspecific datapath intensive CMOS circuits. 2 Landman et al. [8] presented a methodology for low power design space exploration at the architectural level. Black box power models for the architectural level components were generated [9] and used to estimate power while preserving the accuracy of the gate or circuit level estimation. The power analysis tool was ....

P. Landman, "Low-Power Architectural Design Methodologies", Ph.d Thesis, Memorandum No. UCB/ERL M94/62, 30th August 1994.

....the power reduction obtained by isolating a candidate, we shall discuss what parameters affect the power reduction. 4. 1 Parameters Affecting Power Reduction The power consumption of a module can be characterized as a function of the toggle rates at its inputs using socalled macro power models [5, 7]. The toggle rate of a signal is the average number of toggles per clock cycle measured during a simulation of real life test vectors. We assume that for each c i 2 C such a macro power model p i (Tr) as a function of a vector Tr of input toggle rates is available. For an isolation candidate c i ....

P. E. Landman. Low-Power Architectural Design Methodologies. PhD thesis, College of Engineering, University of California, Berkeley, 1994.

....memories are assumed to be on chip. This is a conservative assumption since accesses to off chip memories are very costly in term of energy consumption [11] The simple power model function used in this paper is : P Transfers = E Tr Theta #Transfers Second (1) E Tr = f(#words; #bits) 2) In [25] a function f is proposed to estimate the energy per transfer E Tr in terms of the number of words and the width in bits. Also some possible values for the parameters are provided there. 4. Target architecture This section describes the target architecture on which the initial behavior ....

....border is left out. Array cp is W Theta H = 256 Theta 256 = 65536 times read and written. In total 589824 66564 94 Nachtergaele et al. 65536 65536 = 787460 transfers are performed to the memory for one picture. This would require a memory access time of 42 ns. Using the power model of [25] the energy for one read to a memory of 256 Theta 256 words of eight bit is estimated to be 1.17 Joule. Hence, the power due to 65536 reads is estimated to be 76mWatt. In this way, the power consumption due to memory transfers is estimated to be 727mW for array p and 123 mW for array cp. The ....

Paul Landman. Low-Power Architectural Design Methodologies. PhD thesis, U.C. Berkeley, August 1994.

....we exclude it from the power model. If a memory is offchip, other technologies can be used. We assume memory a lower power 1MB SRAM [11] is used it this case. The simple power model function used in this paper is : P Transfers = E Tr Theta #Transfers Second (1) E Tr = f(#words; #bits) 2) In [12] a function f is proposed to estimate the energy of a transfer E Tr in terms of the number of words and the width in bits. Also some possible values for the parameters are provided there. In this paper we have used more realistic but proprietary vendor models and usually only relative figures can ....

P.Landman, "Low power architectural design methodologies", Doctoral Dissertation, U.C.Berkeley, Aug. 1994.

....a power budget of 0.26 W for 100 MHz operation in all off chip RAMs further on. For lower access frequencies we will scale linearly, which is a reasonable assumption. ffl For the embedded background RAMs, we have used the single port memory power model developed at U.C. Berkeley by Paul Landman [11]. For the parameters in the model, we have scaled down the parameters to a 0.7 technology. Different values for read and write accesses were available and have been used. The input for this model are 3 essential parameters: number of bits, number of words and rate (frequency) at which the RAM is ....

P.Landman, "Low power architectural design methodologies", Doctoral Dissertation, U.C.Berkeley, Aug. 1994.

No context found.

P. Landman, Low power architectural design methodologies, Ph.D Dissertation, U.C. Berkeley, Aug 1994.

No context found.

. P. Landman, "Low-Power Architectural Design Methodologies," Ph.D. dissertation, UC Berkeley, August 1994

No context found.

P.Landman, "Low power architectural design methodologies", Doctoral Dissertation, U.C.Berkeley, Aug. 1994.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC