Digital Equipement Corporation. Alpha AXP Architecture Handbook, October 1994. Home/Search Document Not in Database Summary Related Articles Check |
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Data Prefetching Efficiency on Two Commercial Systems - Acquaviva (1999) (1 citation) (Correct)
....on J for various problem sizes. CRAY systems seem to have fixed this bug [Cra96] Hardware only streams detection can be misleading, as 2 consecutive L2 cache misses initiate a data stream. For example, access to data structure of more than 64 B yield to a stream detection. The Alpha 21164 ISA [Dig94] includes an instruction dedicated to data prefetching (PREF) allowing implementation of various software schemes. But Kessler [Kes94a] noticed that performances can be hurt due to the consumption of MAF entries (Miss Address File) which tends to be a critical resource. The MAF aggregates load ....
Digital Equipement Corporation. Alpha AXP Architecture Handbook, October 1994.
Indirect Branch Prediction using Data Compression Techniques - Kalamatianos, Kaeli (1999) (2 citations) (Correct)
....branches by setting one bit in their 16 bit displacement field to indicate whether they are ST or MT. The displacement field of Alpha indirect branches is not used during instruction execution and is currently filled (whenever possible) by the compiler with hints to allow faster I cache access [43]. Run time detection of MT indirect branches is achieved by 22 recording this bit in each BIU entry and using it every time the same indirect branch is detected at the I fetch stage. The dynamic characteristics of the benchmarks are shown in Table 1. They include the input file, the number of ....
Digital Equipment Corporation, Maynard, Massachusetts. Alpha AXP Architecture Handbook, 1994. 35
Improving the Accuracy of Indirect Branch Prediction via.. - Kalamatianos, Kaeli (1999) (1 citation) (Correct)
....field of an indirect branch of the Alpha AXP ISA. That field is currently filled with 14 bits from a likely target address by the DEC compilers (the other two bits from the 16 bit field are used to indicate the kind of indirect branch) This allows the processor to initiate an early I cache access [31]. In our design we propose using one bit from the displacement field to indicate the type of indirect branch (i.e. ST or MT) This approach has the primary advantage that it does not require any ISA modifications. When the branch is fetched into the processor pipeline, it can be stored as an ....
Digital Equipment Corporation, Maynard, Massachusetts. Alpha AXP Architecture Handbook, 1994.
Improving the Accuracy of Indirect Branch Predication via.. - Kalamatianos, Kaeli (1998) (Correct)
....scheme. The compiler can encode the branch class in the 16 bit memory displacement field of an indirect branch of the Alpha AXP ISA. That field is currently filled with 14 bits from a likely target address by the DEC compiler. This allows the processor to initiate an early I cache access [29] (two bits are used to indicate the kind of indirect branch) In our design we propose using one bit from the displacement field to indicate the type of indirect branch (i.e. ST or MT) This approach has the primary advantage that it does not require any ISA modifications. When the branch is ....
Digital Equipment Corporation, Maynard, Massachusetts. Alpha AXP Architecture Handbook, 1994. 17
Synchronization and Communication in the T3E Multiprocessor - Scott (1996) (52 citations) (Correct)
.... Parallelism may be exposed explicitly, using the message passing model (e.g. Parallel Virtual Machine (PVM) 14] or Message Passing Interface (MPI) 31] or implicitly, using the sharedmemory programming model (e.g. High Performance Fortran (HPF) 19] or the Alpha AXP architectural model [10]) The shared memory model is widely accepted as easier to use, and is better suited for irregular, dynamic parallelism. The message passing model, however, is currently more portable (PVM and MPI run on a wide variety of machines) and makes the detection of parallelism and optimization of data ....
.... meaning that it can be used to construct a wait free implementation 2 of any sequential object (e.g. shared work queues) It is also necessary or beneficial for a variety of scalable synchronization algorithms [30] 32] Load linked store conditional, implemented in several architectures [10][41] 27] is also a universal primitive, and in fact can allow more straight forward implementations of some concurrent objects [18] However, most loadlinked store conditional implementations place restrictions on the types of operations that can be performed in the critical section (e.g. no ....
Digital Equipment Corporation, Alpha AXP Architecture Handbook, 1994.
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