S. Rajan, M. Fujita, K. Yuan, and M. Lee, "High-Level Design and Validation of ATM Switch", Proc. IEEE International High Level Design Validation and Test Workshop (HDLVT'97), Oakland, California, USA, November 1997. Home/Search Document Details and Download
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The Impact of Design Changes on Verification Using MDGs - Zobair, Tahar, Curzon (1999) (Correct)
....tools by property checking and equivalence checking. Lu et al. 10] also formally verified this same ATM switch fabric using VIS. Chen et al. 2] at Fujitsu Digital Technology, formally verified an ATM circuit using SMV. By using a combination of theorem proving and model 2 checking Rajan et al. [11] discovered bugs in a high level ATM model that was presumed correct during simulation. In this report, we investigate whether the formal verification task of an ATM design can be simplified by making necessary design changes: that is whether a notion of Design for Verifiability , similar to ....
S. Rajan, M. Fujita, K. Yuan, and M. Lee, "High-Level Design and Validation of ATM Switch", Proc. IEEE International High Level Design Validation and Test Workshop (HDLVT'97), Oakland, California, USA, November 1997.
Formal Verification of an Asynchronous MAC Layer Protocol in VIS - Peng, Tahar (Correct)
.... (1) formal verification of high layer software protocols, e.g. 6] 2) formal verification of synchronous hardware protocol, e.g. verification of cache coherence protocols in [8] and (3) formal verification of ATM hardware devices (not protocols) e.g. verification of ATM switch in [7] [10]. Our work distinguishes itself from these related publications by the fact that we verify the hardware implementation of an asynchronous high layer protocol (ATMR) We present some techniques on how to simulate the asynchronous ATMR protocol in a synchronous environment and also propose some ....
S. Rajan, M. Fujita, K. Yuan, and M. Lee. High-level design and validation of atm switch. In IEEE International High Level Design Validation and Test Workshop (HLDVT'97), Oakland, California, USA, November 1997.
Comparing HOL, MDG and VIS: A Case Study on the Verification .. - Curzon, Tahar, Lu (Correct)
....state space explosion, they had to abstract the data width of addresses from 8 bits to 1 bit, and the number of addresses in the Write Address FIFO from 168 to 5. Although the design error was diagnosed, there is no proof showing that the abstracted circuit was itself correct. Later, Rajan et al. [25] used a combination of simulation, theorem proving and model checking based on PVS [23] to validate a high level ATM switch model from Fujitsu Ltd. The authors used model checking to verify some control components in the ATM model, and applied exhaustive simulation to verify some operational ....
S. Rajan, M. Fujita, K. Yuan, and M. Lee. High-Level Design and Validation of ATM Switch. In Proceedings of the IEEE International High Level Design Validation and Test Workshop, Oakland, California, November 1997.
PVS Bibliography - Rushby (1998) (2 citations) (Correct)
No context found.
S.P. Rajan, M. Fujita, K. Yuan, and M. T-C. Lee. High-level design and validation of ATM switch. In IEEE International High Level Design Validation and Test Workshop, pages 40--44, Oakland, CA, November 1997. Available at http:// www.csl.sri.com/sree/hldvt97.ps.
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