D Cyrluk, J Rushby, and M Srivas. Systematic formal verification of interpreters. In IEEE International Conference on Formal Engineering Methods (ICFEM'97, pages 140 -- 149, 1997. Home/Search Document Details and Download
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Verifying a Simple Pipelined Microprocessor Using Maude - Harman (2000) (3 citations) (Correct)
....on addressing [industrial] examples within software tools, where an important theme has been e#cient verification strategies. Interesting work on pipelined microprocessor verification includes [25] on AAMP5, a non trivial, industrial example, and its verification in PVS [26] recent accounts are [6, 27]: see also [17] 31] on UINTA, a processor of moderate complexity, and its verification in HOL [12] and [2] on a part of DLX [16] A refinement of the approach in [2] more applicable to out of order systems and long pipelines is [19, 20] In addition, work has been undertaken on the complex ....
D Cyrluk, J Rushby, and M Srivas. Systematic formal verification of interpreters. In IEEE International Conference on Formal Engineering Methods (ICFEM'97, pages 140 -- 149, 1997.
Correctness and Verification of Hardware Systems Using Maude - Harman (2000) (1 citation) (Correct)
....software tools, and hence a key underlying theme of other work has been the need for e#cient verification strategies. Key work on pipelined microprocessor verification includes [25, 26] on AAMP5, a processor of some complexity, and its verification in PVS [27] recent accounts of this work are [6, 28]: see also [17] 32] on UINTA, a processor of moderate complexity, and its verification in HOL [12] and [2] on a a simple three stage ALU pipeline and a fragment of the DLX architecture [16] A refinement of this approach, more applicable to out of order systems and long pipelines is [19, 20] ....
D Cyrluk, J Rushby, and M Srivas. Systematic formal verification of interpreters. In IEEE International Conference on Formal Engineering Methods (ICFEM'97, pages 140 -- 149, 1997.
Algebraic Models of Temporal Abstraction for Initialised Iterated.. - al. (1998) (Correct)
....which identifies those implementation states that should correspond to a specification state. This approach is modified, in a manner similar to that of [42] to cope with pipelining by distributing data in time. Again, in [29, 30] time is not explicitly present. A recent account of this work is [9]. It is not clear that temporal distribution of data (or combination of data and temporal abstraction) is required in practice. Substantial case studies to date (including a superscalar microprocessor in [11, 14] have not required such techniques. Moreover, it may introduce extra complexities. ....
D Cyrluk, J Rushby, and M Srivas. Systematic formal verification of interpreters. In IEEE International Conference on Formal Engineering Methods (ICFEM'97, pages 140 -- 149, 1997.
PVS Bibliography - Rushby (1998) (2 citations) Self-citation (Rushby) (Correct)
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David Cyrluk, John Rushby, and Mandayam Srivas. Systematic formal verification of interpreters. In Michael G. Hinchey and Shaoying Liu, editors, First International Conference on Formal Engineering Methods (ICFEM '97), pages 140--149, Hiroshima, Japan, November 1997. IEEE Computer Society.
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