D. Cyrluk and P. Narendran. Ground temporal logic: a logic for hardware verification. In D. Dill, editor, Computer-Aided Verification (CAV '94), LNCS 818, pages 247--259. SpringerVerlag, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....is to represent hardware designs at different levels of abstraction, and verify the designs hierarchically. Recently, a number of ROBDD extensions such as BMDs [2] and HDDs [7] have been developed to represent arithmetic functions more compactly than ROBDDs. There also emerged a number of methods [8, 5, 11] which verify the overall functionality of Register Transfer Level designs at an abstract level, using abstract variables to denote data signals and uninterpreted function symbols to denote data operations. We have proposed a new class of decision graphs, called Multiway Decision Graphs (MDGs) ....

....statement is generated using symbolic simulation. The algorithm is then used to check its validity. With carefully chosen heuristics for avoiding exponential case splitting, the authors verified a subset of a RISC pipeline processor DLX [5] and a protocol processor (PP) 13] Cyrluk and Narendran [11] defined a first order temporal logic Ground Temporal Logic (GTL) which also uses uninterpreted function symbols. Using a decidable fragment of GTL, they can automate the verification in the PVS theorem prover. These methods, however, are not applicable to verification problems that require ....

D. Cyrluk and P. Narendran. Ground Temporal Logic: A logic for hardware verification. In: D. L. Dill, editor, Computer Aided Verification. Lecture Notes in Computer Science 818, Springer Verlag, 1994.

....of uninterpreted functions. Functions with an infinite domain or range that are not relevant to the properties to be checked are treated symbolically instead of exploring their infinitely many possible evaluations. For model checking hardware systems, uninterpreted functions are used in [BD94,CN94] In our work, we follow the second direction: We introduce a notion for abstract types in the ASM SL. We regard models that comprise abstract types as abstract ASM since functions over these abstract types have no fixed interpretation. We provide a mapping from abstract ASM to Multiway Decision ....

....6 Related Work Uninterpreted functions are addressed elsewhere: In [BD94] data values and operations within the specification of the DLX architecture are modelled by means of uninterpreted functions. However, this approach allows only validity checking, no temporal properties can be checked. CN94] introduce a new logic, called GTL, which also allows uninterpreted functions to be represented. The decidable fragment of GTL can be treated by an automatic validity checker (based on PVS) The thesis of Xu ( Xu99] that introduces the logic and the corresponding model checking algorithm ....

D Cyrluk and P. Narendran. Ground temporal logic: A logic for hardware verification. In D. Dill, editor, Proc. of Int. Conf. on Computer Aided Verification, CAV'94, volume 818 of LNCS, pages 247--259. Springer-Verlag, 1994.

....proof steps: 1) rewriting the property using the design specification, 2) lifting the boolean expression in if then else 8 structures to the top level, and (3) simplification using PVS s BDD and other descision procedures. The specialpurpose decision procedures for microprocessors proposed in [2, 3] are efficient methods for proving such properties under certain restrictions. To accomplish such a transformation of the verification problem, we decomposed the proof of the commuting property into two parts: one that reasons exclusively about the stalling behavior of the pipeline and another ....

D. Cyrluk and P. Narendran. Ground temporal logic---a logic for hardware verification. In David Dill, editor, ComputerAided Verification, CAV '94, volume 818 of Lecture Notes in Computer Science, pages 247--259, Stanford, CA, June 1994. Springer-Verlag.

.... In this regard, we have developed an experimental translator from MurOE [77] to PVS, and have connected a BDD based decision procedure for the modal calculus to PVS, giving us similar capabilities to SMV [78] We are also exploring more efficient approaches to hardware verification [79] [80] and improved support for requirements specifications in the tabular style advocated by Parnas and others [81] 82] Acknowledgments: The work reported here owes a very great deal to our collaborators at NASA Langley Research Center: Rick Butler, Jim Caldwell, Michael Holloway, Paul Miner, and ....

D. Cyrluk and P. Narendran, "Ground temporal logic---a logic for hardware verification", in Computer-Aided Verification, CAV '94, David Dill, Ed., Stanford, CA, June 1994, vol. 818 of Lecture Notes in Computer Science, pp. 247--259, SpringerVerlag.

.... such as model checking have improved considerably: modelcheckers have been able to verify circuits with 10 20 states [3] and have verified the correctness of a PDP11 sized processor [2] special purpose tools have been able to automate the verification of complete benchmark microprocessors [4, 6, 7], language containment methods [10] have also been effectively applied to significant examples. At the other end of the spectrum, the Boyer Moore theorem prover and the HOL theorem prover have been successfully used to verify simple microprocessor [11, 12] Most recently, PVS [16] a higher order, ....

....of the protocol. The theorem prover does the induction and uses abstraction to reduce the inductive step to the two process case which the model checker can quickly decide. 7.2 Other Decidable Theories Other aspects of hardware verification are amenable to different automated tools. All of [4, 6, 7] describe decidable theories or strategies that effectively deal with verification of the data flow through a pipelined microprocessor. The essence of these methods is to use rewriting to generate large IF THEN ELSE expressions that then have to be compared for equality. This comparison is done by ....

D. Cyrluk and P. Narendran. Ground temporal logic--- a logic for hardware verification. In David Dill, editor, Computer-Aided Verification, CAV '94, volume 818 of Lecture Notes in Computer Science, pages 247--259, Stanford, CA, June 1994. Springer-Verlag.

....mappings [1] for the verification of microprocessors and other sequential hardware circuits is commonplace [3, 7, 11] Both automated stand alone tools [3] and automated proof strategies for use in interactive theorem provers [6] have been developed based on the use of abstraction mappings. In [5] we developed a language GTL2 that is appropriate for specifying the correctness of sequential hardware circuits using abstraction mappings. This research was partially supported by SRI International, DARPA contract NAG2703, and NSF grants CCR 8917606, CCR 8915663. Discussions with Deepak ....

....approach is the representation of the specification and implementation machines as transition systems. These transition systems are represented as equations that specify how the state variables are updated by the execution of one machine cycle. These equations are implementation equations in GTL2 [5] and can be stated in the following form. j V j (next(s) next j (s) 3) where V j are state variables, next is the next state function (either I or A in Figure 1) and next j is a function that specifies how state variable V j changes. Additionally, the abstraction mapping is given as ....

D. Cyrluk and P. Narendran. Ground temporal logic---a logic for hardware verification. In David Dill, editor, Computer-Aided Verification, CAV '94, volume 818 of Lecture Notes in Computer Science, pages 247--259, Stanford, CA, June 1994. Springer-Verlag.

....cycles into the future. See [11,24] for details. If the abstraction mapping is given this way, then once the proof is split according to the definition of num cycles, the resulting statement of correctness is usually an instance of a decidable fragment of the theory Ground Temporal Logic (GTL2) [10]. The problem is to come up with an effective procedure for deciding this theory. One obvious strategy is to completely rewrite the next state functions and abstraction mapping until a large IF THEN ELSE is generated, then perform a case analysis on the resulting expression and check that each ....

D. Cyrluk and P. Narendran. Ground temporal logic---a logic for hardware verification. In David Dill, editor, Computer-Aided Verification '94, pages 247--259. Volume 818 of Lecture Notes in Computer Science, Springer-Verlag, 1994.

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D. Cyrluk and P. Narendran. Ground temporal logic: a logic for hardware verification. In D. Dill, editor, Computer-Aided Verification (CAV '94), LNCS 818, pages 247--259. SpringerVerlag, 1994.

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D. Cyrluk and P. Narendran. Ground temporal logic: a logic for hardware verification. In D. Dill, editor, Computer-Aided Verification (CAV '94), LNCS 818, pages 247--259. Springer-Verlag, June 1994. 45

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D. Cyrluk and P. Narendran. Ground temporal logic: a logic for hardware verification. In D. Dill, editor, Computer-Aided Verification (CAV '94), LNCS 818, pages 247--259. SpringerVerlag, 1994.

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D. Cyrluk and P. Narendran. Ground temporal logic---a logic for hardware verification. In David Dill, editor, Computer-Aided Verification, CAV '94, volume 818 of Lecture Notes in Computer Science, pages 247--259, Stanford, CA, June 1994. Springer-Verlag.

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