R. Harper, J. Lala, and J. Deyst. Fault tolerant parallel processor architecture overview. In Symp. on Fault-Tolerant Computing, pages 252--257. IEEE, June 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....sends the result in its buffer to the user, and the algorithm is terminated. 4 Discussion Replication and majority voting are the conventional methods for achieving fault tolerance in distributed systems. Distributed voting has become the strategy of choice, and has had a number of incarnations [12, 13, 14]. Heavy reliance has been placed on the 2 phase commit protocol [8] in which the voters first exchange votes and independently determine the majority result, and then one arbitrary voter within the majority commits this value to the user. This method is widely advocated in designing ....

Harper, R. E., Lala, J. H., and Deyst, J. J., "Fault Tolerant Parallel Processor Architecture Overview," Proceedings of the 18th Fault-Tolerant Computing Symposium, June, 1988, pp. 252-257.

....methods for achieving fault tolerance in distributed systems. Decentralized voting, in which the replicated voters independently determine the majority rather than relying on a central server to tally the results, has become the strategy of choice, and has had a number of incarnations [7, 8, 9]. Most of these systems have used the 2 phase commit protocol in order to implement the voting scheme. In this protocol, the replicated voters first exchange their votes and independently determine the majority result. Once a final result has been calculated, one of the voters is arbitrarily ....

Harper, R. E., Lala, J. H., and Deyst, J. J., "Fault Tolerant Parallel Processor Architecture Overview," Proceedings of the 18th Fault-Tolerant Computing Symposium, June, 1988, pp. 252-257.

....architectures, where the system activities are initiated as a consequence of the occurrence of external or internal events. Event triggered real time architectures are assumed to provide a high degree of flexibility and have therefore received considerable attention in the literature (FTPP [4], ARTS [27] MAFT [7] Because of their event triggered nature, however, an excessive number of possible behaviors must be analyzed in order to establish timeliness guarantees. Furthermore, the implementation of active redundancy by the replication of the components is hard because of the issue ....

R. E. Harper, J. H. Lala, and J. J. Deyst. Fault tolerant parallel processor architecture overview. In Proc. 18th Int. Symposium on Fault-Tolerant Computing, pages 252--257, Tokyo, Japan, June 1988.

....as nuclear power plant control systems [9] factory automation systems, space vehicles, and air traffic control systems. These systems tend to require a lot of computation power and, hence, providing concurrent execution of multiple tasks via parallel and distributed computations is inevitable [2]. Also, another trend that can be observed is the integration of transaction processing capabilities within these process control systems since many of them require a large state space. Due to the above characteristics of many potential applications, limitations in existing approaches prevent ....

R.E. Harper, J.H. Lala, and J.J. Deyst, "Fault Tolerant Parallel Processor architecture overview," 18th Intl. Symp. on Fault-Tolerant Computing, Tokyo, Japan, June 1988, pp. 252-257.

....value using m=u degradable agreement. This conjecture is being investigated currently. The reader can verify that the impossibility result in [5] does not as such apply to the above problem. 6. 2 Traditional Clock Synchronization One solution, applicable to systems such as FTMP, NETS [11] and FTP [4], is the use of hardware clock synchronization (as opposed to software algorithms) In typical systems, the complexity and cost of clock hardware is orders of magnitude lower as compared to the processor (or node) complexity. Therefore, the failure rates for clock hardware are likely to be ....

R. E. Harper, J. H. Lala, and J. J. Deyst, "Fault tolerant parallel processor architecture overview," in Digest of papers: The 18 th Int. Symp. Fault-Tolerant Comp., pp. 252--257, 1988.

....BYZ within bounded time, it is not a necessary condition. Section 6.3 presents another solution that terminates BYZ within a bounded amount of time, up to u faults, using the physical clocks. 6. 2 Traditional Clock Synchronization One solution, applicable to systems such as FTMP, NETS [11] and FTP [5], is the use of hardware clock synchronization (as opposed to software algorithms) In typical systems, the complexity and cost of clock hardware is orders of magnitude lower as compared to the processor (or node) complexity. Therefore, the failure rates for clock hardware are likely to be ....

R. E. Harper, J. H. Lala, and J. J. Deyst, "Fault tolerant parallel processor architecture overview," in Digest of papers: The 18 th Int. Symp. Fault-Tolerant Comp., pp. 252--257, 1988.

....computer systems for over two decades. During this time, CSDL became interested in the use of formal methods to increase confidence in their designs. ORA was given the task of formally specifying and verifying a key circuit (called the scoreboard) of the Fault Tolerant Parallel Processor (FTPP) [53] in Clio [132] The formal verification uncovered previously unknown design errors. When the scoreboard chip was fabricated, it worked without any error manifestation. It was the first time that CSDL produced a chip that worked perfectly on a first fabrication. CSDL credits VHDL development ....

Harper, Richard E.; Lala, Jay H.; and Deyst, John J.: Fault Tolerant Parallel Processor Architecture Overview. In Proceedings of the 18th Symposium on Fault Tolerant Computing, 1988, pp. 252--257.

....computer systems for over two decades. During this project, CSDL became interested in the use of formal methods to increase confidence in their designs. ORA was given the task of formally specifying and verifying a key circuit (called the scoreboard) of the Fault Tolerant Parallel Processor (FTPP) [48] in Clio [114] The formal verification uncovered previously unknown design errors. When the scoreboard chip was fabricated, it worked without any error manifestation. It was the first time that CSDL produced a chip that worked perfectly on a first fabrication. CSDL credits VHDL development ....

Harper, Richard E.; Lala, Jay H.; and Deyst, John J.: Fault Tolerant Parallel Processor Architecture Overview. In Proceedings of the 18th Symposium on Fault Tolerant Computing, 1988, pp. 252--257.

....computer systems for over two decades. During this project, CSDL became interested in the use of formal methods to increase confidence in their designs. ORA was given the task of formally specifying and verifying a key circuit (called the scoreboard) of the Fault Tolerant Parallel Processor (FTPP) [67] in Clio [68] The formal verification uncovered previously unknown design errors. When the scoreboard chip was fabricated, it worked without any error manifestation. It was the first time that CSDL produced a chip that worked perfectly on a first fabrication. CSDL credits VHDL development tools ....

Richard E. Harper, Jay H. Lala, and John J. Deyst, "Fault tolerant parallel processor architecture overview", in Proceedings of the 18th Symposium on Fault Tolerant Computing, pp. 252--257, 1988.

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R. Harper, J. Lala, and J. Deyst. Fault tolerant parallel processor architecture overview. In Symp. on Fault-Tolerant Computing, pages 252--257. IEEE, June 1988.

No context found.

Harper, R. E., Lala, J. H., and Deyst, J. J., "Fault Tolerant Parallel Processor Architecture Overview," Proceedings of the 18th Fault-Tolerant Computing Symposium, June, 1988, pp. 252-257.

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