J S. Moore. Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor. Tech. Rept. NASA CR-189588, NASA, 1992.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....of the total are faulty. 3 Previous Formalizations of OM Bevier and Young[2] published a formalization and proof of the Oral Messages algorithm using the Boyer Moore Nqthm[4] theorem prover in the context of a larger project of building a verified circuit implementing interactive consistency [1, 10]. They also mechanically checked the Lamport, et al. proof that the Oral Messages algorithm is optimal among its class of algorithms. Bevier and Young reported of their proof: The proofs of lemmas IC1 and IC2 are a fairly difficult exercise in mechanical theorem proving. In one sense, there was ....

J S. Moore. Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor. Technical Report Technical Report 69, Computational Logic, Inc., 1717 W. Sixth Street, Suite 290, Austin, TX 78703, August 1991.

.... algorithms [11, 20, 12] as well as verified specifications of high level system descriptions [6, 7, 16, 23] In addition, there have been exercises demonstrating the application of mechanical theorem provers to the verification of hardware components realizing faulttolerant algorithms [22, 1, 13]. The difficulty with these verified components is that each proof involves simplifying assumptions concerning the rest of the architecture. In particular, they assume that the redundant computing elements are operating in lock step synchrony. While it is possible to achieve this using existing ....

J Strother Moore. Mechanically verified hardware implementing an 8-bit parallel io byzantine agreement processor. NASA Contractor Report 189588, April 1992.

....most difficulty convincing themselves they ve got right. In the first years of the program, formal specifications and verifications for these building blocks were undertaken and completed in the following systems: EHDM and later in PVS at SRI [55, 50, 59] Nqthm, the Boyer Moore prover, at CLI [1, 2, 45, 44, 68]; and Clio and the Penelope Ada verification system at ORA [61, 4, 63, 30, 62] Concurrently we gained experience at Langley using a number of the prover systems including EHDM, Nqthm, and HOL. During that time we were primarily occupied with the design and verification (in EHDM) of a ....

J Strother Moore. Mechanically verified hardware implementing an 8bit parallel io byzantine agreement processor. NASA Contractor Report 189588, April 1992.

....to our tool kit an integrated verification environment for a subset of a commercial hardware description language, including features for analyzing fanout, gate delay, loads and drives. The reusable library for this language has since been used to verify the design of a Byzantine agreement chip [6]. Because we formalized LSI Logic s NDL we can also use commercial tools to analyze our hardware designs. We have used Nqthm to verify the logical and some performance properties of chip designs and then used LSI Logic tools to do electrical analysis, layout, schematic liberation, and fabrication. ....

....hardware designs. We have used Nqthm to verify the logical and some performance properties of chip designs and then used LSI Logic tools to do electrical analysis, layout, schematic liberation, and fabrication. This is another example of the application of different tools to the same problem. See [6] for an example. Upon the fabrication of the FM9001, we ported the old stack proof to the new machine using Nqthm. This required modifying the linker so as to generate the binary appropriate for the new machine. Other changes were made in anticipation of actually running the device (e.g. we ....

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J S. Moore, "Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor", Tech. report Technical Report 69, Computational Logic, Inc., 1717 W. Sixth Street, Suite 290, Austin, TX 78703, August 1991.

.... algorithm using the Boyer Moore theorem prover [52] They also implemented this algorithm down to the register transfer level and demonstrated that it implements the mathematical algorithm [53] and then subsequently verified the design down to a hardware description language HDL developed at CLI [54]. A more efficient mechanical proof of the oral messages algorithm was also developed by SRI[55] ORA also investigated the formal verification of Byzantine Generals algorithms. They focused on the practical implementation of a Byzantine resilient communications mechanism between Mini Cayuga ....

J Strother Moore, "Mechanically verified hardware implementing an 8-bit parallel io byzantine agreement processor", NASA CR-189588, Apr. 1992.

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J S. Moore. Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor. Tech. Rept. NASA CR-189588, NASA, 1992.

....possible to verify an implementation of each processor independently of the other and of the model of asynchrony. Consider send. It is the formal specification of the kernel of the send side of a microprocessor s communications module. Indeed, its definition was developed with that use in mind. See[Moo92b]. Using the Formal HDL described in[BH90] it is possible to design a circuit that implements send. The formal semantics of the A Formal Model of Asynchronous Communication 29 HDL is cast as an Nqthm interpreter (or simulator) that determines the signals on all the pins and the state produced ....

....on a given pin over some number of cycles starting from a given initial state is equal to the sequence of signals produced by send. Proving such a correctness result would be straightforward (given the reusable theory developed for the Formal HDL by Brock and Hunt) for some hardware designs. See[Moo92b] for an example of the use of the Formal HDL in the specification and design of a simple verified microprocessor. In an exactly analogous fashion, one could design a digital phase locked loop alleged to implement recv and prove that it was correct. Phase locking is the idea of adjusting the ....

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Moore, J S.: Mechanically verified hardware implementing an 8-bit parallel io byzantineagreement processor. Technical Report NASA CR-189588, NASA, 1992. J Strother Moore

....about programs in that language. The development of reasoning tools for standard languages such as VHDL will undoubtedly remove some of the necessity of rolling your own formal semantics. The Brock Hunt NDL formalization for FM9001, for example, can be reused to verify other hardware designs [18]. But as long as microprocessors support new, special purpose machine languages i.e. as long as designers produce specialpurpose microprocessors such as the now old fashioned BDX930, or the brand new AAMP5 and CAP formal mechanical verification will require the formalization of new ....

J S. Moore. Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor. Technical Report NASA CR-189588, NASA, 1992.

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J S. Moore. Mechanically Verified Hardware Implementing an 8-bit Parallel IO Byzantine Agreement Processor. Technical Report Technical Report 69, Computational Logic, Inc., 1717 W. Sixth Street, Suite 290, Austin, TX 78703, August 1991.

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