E. Macii, M. Pedram and F. Somenzi, "High level power modeling, estimation and optimization", IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, November 1998, pages 1061-1079.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... design [5] After that, optimization intensive techniques have been first proposed for behavioral synthesis in statically scheduled systems [6] Next, techniques have been proposed for power minimization in systems with dynamic behavior [7] and for operating system level power programmable systems [8]. In addition, variable voltage techniques started to gain popularity [9] More recently, centralized techniques for power minimization attracted a great deal of attention [10] Most recently, several approaches that use only local information for power management in WANs have been proposed. Our ....

E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation, and optimization," in ACM/IEEE DAC, 1997, pp. 504--511.

....policies centered only at the device and VLSI levels are no longer sufficient. As a result, power has propagated as an important design constraint to the higher levels. The reader can find further information and surveys regarding system level power aware design in the following articles [25] [26], 27] 28] 29] 30] 31] W cm 1 10 100 1000 386 Pentium PentiumII PentiumIV Nuclear Reactor PentiumIII PentiumPro 486 Fig. 1. Power Density of Intel Chips (Source: Fred Pollack [24] III. LAYER BY LAYER SURVEY ON SYSTEM LEVEL POWER AWARE REAL TIME RESEARCH Processors used in ....

E. Macii, M. Pedram, F. Somenzi, "High-Level Power Modeling, Estimation and Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 17, no 11, pp. 10611079, Nov. 1998.

....and accuracy of the macro modeling approach DMA Orig. I Macromodeling Speedup Error sze Energy CPU [ Energy CPU (mJ) t me (s) mJ) t me (s) 2 0.54 8051.52 0.72 92.44 87. I 32.9 4 0.44 4023.36 0.56 63.46 63.4 27.4 8 0.39 2080.77 0.48 48.73 42.7 23.7 16 0.36 1398.49 0.44 41.08 34.0 21.6 32 0. 35 852.25 0.42 37.71 22.6 20.4 64 0.34 680.78 0.41 36.02 18.9 19.6 The tables indicate that: The acceleration technique based on caching results in simulation speedups of between 8.6X and 18.8X (average of 13X compared to the base case without any acceleration technique. The macro modeling ....

....and accuracy of the macro modeling approach DMA Orig. I Macromodeling Speedup Error sze Energy CPU [ Energy CPU (mJ) t me (s) mJ) t me (s) 2 0.54 8051.52 0.72 92.44 87. I 32.9 4 0.44 4023.36 0.56 63.46 63.4 27.4 8 0.39 2080.77 0.48 48.73 42.7 23.7 16 0.36 1398.49 0.44 41.08 34.0 21.6 32 0. 35 852.25 0.42 37.71 22.6 20.4 64 0.34 680.78 0.41 36.02 18.9 19.6 The tables indicate that: The acceleration technique based on caching results in simulation speedups of between 8.6X and 18.8X (average of 13X compared to the base case without any acceleration technique. The macro modeling based ....

[Article contains additional citation context not shown here]

E. Macii, M. Pedram. and E Somenzi, "High-level power modeling, estimation, and optimization," in Proc. Design Automation Conf., pp. 504-511. June 1997.

....tools, that provide accurate and reliable results at various levels of abstraction. Power analysis tools are available primarily at the gate and circuit levels, and not at the architecture and algorithm levels where they could really make an impact. Current research is trying to fill this gap [33][43][86] 2.2.4 How much is a picojoule In Table 3 we compare the energy of a transition of a CMOS gate (about 1 picojoule) with a variety of energy quantities. Note that neural transitions are an order of magnitude more efficient (in average) An assignment consumes about 100 picojoules for a ....

.... be applied to replace energy consuming operations by a combination of simpler operations (for example by replacing multiplications into shift and add operations) Drawbacks of this approach are that it introduces extra overhead for registers and control, and that it may increase the critical path [43]. 2.5.6 Energy reduction in communication Up to this point we have mainly discussed the techniques that can be used to decrease the energy consumption of digital systems and focussed on computer systems. In this subsection we will discuss some techniques that can be used to reduce the energy ....

Macii, E., Pedram M., Somenzi F.: "High-level power modeling, estimation, and optimization", IEEE transactions on computer-aided design of integrated circuits and systems, Vol. 17, No. 11, pp. 1061-1079, November 1998.

....costs and lessens the reliability of the circuit. A lot of techniques have already been proposed to take power consumption into account in high level synthesis. Among them are optimizations like algebraic transformations, usage of multiple supply voltages, loop transformations etc. See [2] for detailed overview. In the extremely complex design of microelectronic circuits, the problem of estimating the effects of different design alternatives on the power dissipation arises. Design decisions made in a very early phase of the development process, in which the design ....

E. Macii, M. Pedram, F. Somenzi, "High Level Power Modeling, Estimation, and Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(11), pp. 1061 -- 1079, November

....inserted. Due to this, a program may have longer execution time, but still consume less energy than before. An example program will be given in this work. 2 Related Work An overview of hardware and software based methods for reducing the energy consumption of electronic systems can be found in [8]. Some of these can be integrated into the compiler and thus reduce energy consumption without any hardware changes. The compiler optimization technique register pipelining [1,2,9] belongs to this class of software methods and deals with memory accesses. It reduces the number of memory accesses ....

Macii, E. and Pedram, M. and Somenzi, F.,"High-Level Power Modeling, Estimation, and Optimization",IEEE, Trans. on CAD of ICs and Systems, November 1998

.... is the speed of estimation, which must be fast enough to allow the exploration of many alternative design implementations in other words, an estimator that takes several hours (or minutes) to execute, will not be suitable in a system requiring hundreds (or thousands) of design iterations[20 22]. These systems attempt to model the power consumption of design units (such as adders or multipliers) which are combined in the power estimator to build up a complete system level power figure. Factors such as data distribution, signal correlation and glitching activity are addressed [21] but ....

Macii, E., Pedram, M., Somenzi, F., "High-Level Power Modeling, Estimation, and Optimization", Design Automation Conference, 1997.

.... u , where T u is a reasonably large integer and can be estimated for the required fault coverage using the techniques from [39] The power dissipation for registers, adders and multipliers are assumed to be P R = P u , P = P u and P = 4 P u where P u can be derived using the techniques from [40] or it can be computed for each module using given pseudorandom sequences that achieve the required fault coverage. To assess the effectiveness of the proposed techniques, PC TSS and TA TSS have been compared for different power constraints ranging from 12 P u to 19 P u . The generic high level ....

E. Macii, M. Pedram, and F. Somenzi, "High level power modeling, estimation, and optimization," IEEE Transactions on CAD, vol. 17, pp. 1061--1079, Nov 1998.

....designs and much work has been done in this area as surveyed in [1] While power reduction techniques can be applied at nearly every design abstraction level, many previous works have focused on the lower levels of abstraction. Recently, there is a focus on power reduction at the higher levels [2] where large power savings are possible merely by cutting down on wasted power. High level power reduction mainly involves shutting down unnecessary portions of the circuit, thereby reducing the total amount of switching activities. Two areas of shutdown techniques for power reduction have ....

Enrico Macii, Massoud Pedram, & Fabio Somenzi, "High-Level Power Modeling, Estimation, and Optimization," Proceedings of the Design Automation Conference, pp. 31-38, 1997.

....design and much work has been done in this area, as surveyed in [1] While power reduction techniques can be applied at nearly every design abstraction level, many previous works have focused on the lower levels of abstraction. Recently, there is a focus on power reduction at the higher levels [2] where large power savings are possible merely by cutting down on wasted switching activities. It has been found that the dynamic power due to capacitive charging and discharging as calculated from the equation P d = 1 2 C V 2 f N (1) where C is the loading capacitance in the circuit, V is ....

Enrico Macii, Massoud Pedram, & Fabio Somenzi, "High-Level Power Modeling, Estimation, and Optimization," Proceedings of the Design Automation Conference, pp. 31-38, 1997.

....design and much work has been done in this area, as surveyed in [1] While power reduction techniques can be applied at nearly every design abstraction level, many previous works have focused on the lower levels of abstraction. Recently, there is a focus on power reduction at the higher levels [2] where large power savings are possible merely by cutting down on wasted switching activities. Two areas of shutdown techniques for power reduction have appeared in recent literature. In datapath shutdown techniques, portions of the combinational logic in the datapath can be shut down for some ....

Enrico Macii, Massoud Pedram, & Fabio Somenzi, "High-Level Power Modeling, Estimation, and Optimization," Proceedings of the Design Automation Conference, pp. 31-38, 1997.

....components (application specific hardware, embedded software, memory hierarchy, buses, etc. separately. Various power estimation and minimization techniques for hardware at the transistor, logic, architecture, and algorithm levels have been developed in the recent years, and are summarized in [1, 2, 3, 4, 5]. Power analysis techniques have been proposed for embedded software based on instruction level characterization [6] and simulation of the underlying hardware [7] Power estimation and optimization techniques for other system on chip components, including memory hierarchies and system buses, have ....

....exploration. This section describes novel techniques that can be employed to improve the efficiency of the power coestimation process, while attempting to keep the loss in accuracy as low as possible. 4. 1 Macromodeling The idea of macro modeling is derived from RT level hardware power estimation [2, 18, 5]. In this section, we illustrate how we have applied the idea of macro modeling to embedded software. However, the approach in the case of hardware is quite similar. 3 In Proc. Design Automation and Test Europe (DATE) 64 2000 Target compiler object files for target uP uC synthesis ....

[Article contains additional citation context not shown here]

E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation, and optimization," in Proc. Design Automation Conf., pp. 504--511, June 1997.

....cost functions or approximation formulas. In section 6, we apply our algorithm on a real GPS navigation system. In the remainder of the paper, we state future work and give our conclusion. 2. Previous Work Much work has been done in modeling and estimating power in IC design at a high level [3, 8]. These modeling and estimation techniques assume one average circuit capacitance for both internal and external power computations. We separate these two components, in our estimations, to account for buses with much larger capacitance compared to the internal circuits. Other work has looked at ....

Enrico Macii, Massoud Pedram, Fabio Somenzi, "High-Level Power Modeling, Estimation and Optimization," in Proceedings of DAC, pp. 504-511, 1997.

.... heuristics that trade o# runtime with quality [1] package module size constraints through structural partitioning of the processor [2] and time multiplexing I O signals over wires [3] and power consumption through isolation of processor sub circuits to avoid unnecessary signal switching [4]. We previously hypothesized that functional partitioning could address many such problems simultaneously. In functional partitioning, we first divide a large process into smaller mutually exclusive sub processes, and then synthesize a sub processor for each sub process, resulting in communicating ....

E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation and optimization," in Proceedings of the Design Automation Conference, 1997.

....that the challenge of high level power estimation is to find models that provide sufficient accuracy while keeping the number of elements in the summation of Equation 1 as small as possible. Overviews of methods for high level power estimation can be found in recently published review papers [16] [17], 18] Many methods for high level power estimation make use of macro models. These are functional descriptions that compute power values for specific hardware modules (functional units, memories, etc. as a function of module parameters (e.g. word lengths) and statistical parameters related to ....

E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation and optimization," in 34th Design Automation Conference, 1997, pp. 504--511.

....cost functions or approximation formulas. In section 6, we apply our algorithm on a real GPS navigation system. In the remainder of the paper, we state future work and give our conclusion. 2. Previous Work Much work has been done in modeling and estimating power in IC design at a high level [3, 8]. These modeling and estimation techniques assume one average circuit capacitance for both internal and external power computations. We separate these two components, in our estimations, to account for buses with much larger capacitance compared to the internal circuits. Other work has looked at ....

Enrico Macii, Massoud Pedram, Fabio Somenzi, "High-Level Power Modeling, Estimation and Optimization," in Proceedings of DAC, pp. 504-511, 1997.

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E. Macii, M. Pedram and F. Somenzi, "High level power modeling, estimation and optimization", IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, November 1998, pages 1061-1079.

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E. Macii, M. Pedram and F. Somenzi, `High level power modeling, estimation and optimization', IEEE Trans. on Computer Aided Design, 17(11):1061-1079, 1998.

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E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation and optimization," IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, pp. 1061-1079, Nov. 1998.

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E. Macii, M. Pedram and F. Somenzi, "High level power modeling, estimation and optimization," IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, pp. 1061-1079, Nov. 1998.

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E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation, and optimization," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1061--1079, Nov. 1998.

....algorithms of Sections VI and VII strive for satisfying all the above requirements. V. RELATED WORK The development of computer aided design techniques for power minimization has been a very active area of research in the last few years (refer to the surveys by Pedram [9] and by Macii et al. [10] for further reading) Our paper is related to a number of sequential power optimization techniques that are briefly summarized next. FSM decomposition for low power [11] 14] can be seen as a top down computational kernel extraction procedure that starts from explicit STG specifications (i.e. ....

E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation, and optimization," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1061--1079, Nov. 1998.

....system, the attention of designers is focused on the minimization of the power dissipated by the circuitry that performs the required computations. Accurate and efficientpower models for digital circuits at various levels of abstraction have been developed to support design space exploration [1]. Unfortunately, much less attention has been dedicated to power supply models. In many cases, it is implicitly assumed that the power supply provides a constantvoltage and delivers a fixed amountofenergy. This assumption is not valid in the case of battery operated devices. Even though power ....

E. Macii, M. Pedram, F. Somenzi, "High-Level Power Modeling, Estimation, and Optimization," IEEE Trans. on CAD, Vol. 17, No. 11, pp. 1061-1079, Nov. 1998.

....report, the macromodel calibration process would be a lot simpler since the required information would be available. Our technique handles both super scalar and pipelined processors. However, it is not intended to replace the works that are exemplified by [2] and [3] Please refer to [4][5] for detailed reviews of high level (including software level) power estimation and optimization. An instruction is active if it is being executed in the instruction pipeline of a given microprocessor. The power microanalysis for the microprocessor can be defined as identifying what active ....

E. Macii, M. Pedram and F. Somenzi, "High level power modeling, estimation and optimization," IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, pages 1061-1079, Nov. 1998.

....This is in agreement with the vast majority of work of other researchers who also considered only external capacitance charging and discharging in their power models. Existing techniques for power estimation at gate and circuit level can be divided in two main classes: dynamic and static [1] [25]. Dynamic techniques [2] 3] explicitly simulate the circuit under a typical input stream. Consequently, their results depend on the simulated sequence, and the required number of simulated vectors is usually high. These techniques can provide sufficient accuracy at the expense of large running ....

E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation, and optimization," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1061--1079, Nov.

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E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation and optimization," in Proc. Design Automation Conf., 1997.

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E. Macii, M. Pedram, F. Somenzi, "High-Level Power Modeling, Estimation and Optimization," IEEE Trans. on CAD of Integrated Circuits and Systems., 1998.

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E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation, and optimization", IEEE Trans. Computer-Aided Design of Integrated Circuits and Syst. 17, 11 (1998) 1061--1079.

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E.Macii, M.Pedram and F.Somenzi, "High-Level Power Modeling, Estimation, and Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, n. 11, pp. 1061-1079, 1998.

No context found.

Macii, E. and Pedram, M. and Somenzi, F.,"High-Level Power Modeling, Estimation, and Optimization",IEEE, Trans. on CAD of ICs and Systems, November 1998

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E. Macii, M. Pedram, and F. Somenzi, "High-level power modeling, estimation and optimization," in 34th Design Automation Conference, 1997, pp. 504--511.

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