Russinoff, D., Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits, forthcoming technical report, Computational Logic, Inc. Home/Search Document Details and Download
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Design Goals for ACL2 - Kaufmann, Moore (1994) (24 citations) (Correct)
....transduces the waveform written by one processor into that read by an independently clocked processor, as a function of the phases and rates of the two clocks and the communications delay. The correcntess of a gate level design of a device implementing the biphase mark protocol has been proved [32]. The correctness of a gate level design of a device implementing an 8 bit parallel io Byzantine agreement processor has been proved [26] In addition, it was proved that the algorithm implemented by the Byzantine agreement processor correctly solves the oral messages problem [5] Finally, the ....
D. M. Russinoff. Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits. Technical Report 99, Computational Logic, Inc., Austin, Texas, May, 1994.
ACL2: An Industrial Strength Version of Nqthm - Kaufmann, Moore (1996) (30 citations) (Correct)
....in this document are those of the author(s) and should not be interpreted as representing the official policies, either expressed or implied, of Computational Logic, Inc. the Defense Advanced Research Projects Agency, the Office of Naval Research, or the U.S. Government. earlier systems [3, 4, 5, 8, 10, 11, 13, 14, 15, 18, 19, 20, 29, 31, 32, 35, 36, 37, 38, 41, 42, 43] supports the claim that such a logic is sufficiently expressive to permit one to address deep mathematical problems and realistic verification projects. The fact that the Nqthm logic is executable is also an important asset when using it to model hardware and software systems: the models can be ....
D. M. Russinoff. Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits. Technical Report 99, Computational Logic, Inc., Austin, Texas, May, 1994. URL http://www.cli.com/.
A Formalization of a Subset of VHDL - Russinoff (1994) (1 citation) Self-citation (Russinoff) (Correct)
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Russinoff, D., Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits, forthcoming technical report, Computational Logic, Inc.
A Formalization of a Subset of VHDL - Russinoff (1993) (1 citation) Self-citation (Russinoff) (Correct)
....respectively. In the simulation displayed in Figure 4, for example, the input is constant over the interval [20000; 40000) and hence the computed value of L is valid on the interval [32000; 44000) The generalization of this proposition to to arbitrary combinational circuits is straightforward [4]. Similar reasoning may be applied to state holding (i.e. cyclic) circuits. An analysis of an interesting class of such circuits, based on the flip flop dff of Section 5, may be found in [4] Here we consider only the basic flip flop itself. A Formalization of a Subset of VHDL Technical Report ....
....44000) The generalization of this proposition to to arbitrary combinational circuits is straightforward [4] Similar reasoning may be applied to state holding (i.e. cyclic) circuits. An analysis of an interesting class of such circuits, based on the flip flop dff of Section 5, may be found in [4]. Here we consider only the basic flip flop itself. A Formalization of a Subset of VHDL Technical Report #98 21 D CLK Q 40 80 Figure 5: Simulation of dff The intended behavior of this device depends on the assumptions that the CLK input behaves as a regular clock pulse and that the value of ....
Russinoff, D., Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits, forthcoming technical report, Computational Logic, Inc.
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