R.K. Ranjan, J.V. Sanghavi, R.K. Brayton, and A. Sangiovanni-Vincentelli, "High performance BDD package based on exploiting memory hierarchy," in Proc. Design Automation Conference (DAC), Las Vegas, NV, June 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....the number of its nodes. Various packages have been developed to manipulate OBDDs: Somenzi s CUDD from Colorado University [Som01] Lind Nielsen s BuDDy, Biere s ABCD, Janssen s OBDD package from Eindhoven University of Technology, Carnegie Mellon s OBDD package, the CAL package from Berkeley [SRBSV96] K. Milvang Jensen s parallel package BDDNOW, Yang s PBF package. All these packages are endowed with a number of built in operations which allow to manipulate the OBDDs and to combine them. Here we are interested in some of these operations: the equality test, the Boolean operations [ n, ....

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance bdd package based on exploiting memory hierarchy. In Proc. of ACM/IEEE Design Automation Conference, 1996.

.... for which there is no sub exponential BDD representation [22] Not surprisingly, nding an optimal order is computationally hard problem [14] The BDDs constructed in the course of veri cation grow extremely large, resulting in space outs or severe performance degradation due to paging [73]. Symbolic approaches based on BDDs are limited to designs containing on the order of a few hundred state elements. Of course, certain designs containing thousands of latches have been veri ed; typically, they are extremely regular, and are very much the exception rather than the normal. Many ....

R. Ranjan, J. Sanghavi, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. High Performance BDD Package Based on Exploiting Memory Hierarchy. In Proc. of the Design Automation Conf., Las Vegas, NV, June 1996.

....normally becomes so severe as to prevent termination. One approach to increase locality of reference in BDD manipulation consists of using contiguous memory locations for all the nodes labeled by the same variables and processing all the nodes for one variable before moving to another variable [48, 2, 55, 61]. This approach is commonly referred to as breadth first processing of BDDs, though it is properly levelized processing. The algorithm for levelized calculation of a generic boolean connective is shown in Figure 18. It consists of two passes: During the fist, top down pass requests are generated ....

....for the request queues may thus offset the advantages of the increased locality of access. Combining the levelized approach with the conventional recursive one can substantially alleviate the problem [61] Additional speed up techniques including superscalarity and pipelining are described in [55]. Reordering tends to destroy the segregation of nodes according to the variables. The typical approach is to restore such segregation after every reordering. The levelized approach to BDD manipulation is quite effective in reducing the number of page faults. When the processes fit in main memory ....

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance BDD package based on exploiting memory hierarchy. In Proceedings of the Design Automation Conference, pages 635--640, Las Vegas, NV, June 1996.

....Now we look at some example circuits to see the flexibility we have in choosing the core. In this thesis, we are using a subset of the ISCAS89 benchmark circuits [12] to demonstrate the synthesis techniques. We use binary decision diagrams (BDDs) and a standard toolset (similar to the ones in [7, 51, 68]) to implement our algorithms. Because of limitations imposed by the use of the BDD package we use the subset of ISCAS89 circuits 2 2 We use the benchmark circuits supplied with the SIS package, version 1.2. For some inexplicable reason, at least two of the benchmark circuits, s208 and s420 seem ....

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. High Performance BDD Package Based on Exploiting Memory Hierarchy. In Proc. of the Design Automation Conf., Las Vegas, NV, June 1996.

.... represent and manipulate the state spaces of designs [14] The primary limitation of BDD based approaches to invariant checking is that for many designs, the BDDs constructed in the course of verification grow extremely large, resulting in space outs or severe performance degradation due to paging [15]. Practicing verifiers are less concerned with providing formal proofs of correctness for their designs than they are with finding bugs in them as early as possible; this is attested to by the complete lack of penetration of theorem provers in the hardware verification community. Indeed, ....

R. Ranjan, J. Sanghavi, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. High Performance BDD Package Based on Exploiting Memory Hierarchy. In Proc. of the Design Automation Conf., Las Vegas, NV, June 1996.

....can significantly improve the overall performance. Improving the efficiency of memory access can take place at many levels of the hardware memory hierarchy. Memory access locality may be improved for the cache, translation lookaside buffer (TLB) or main memory. Ochi [15] Ashar [2] and Sanghavi [17] have addressed the problem of page locality by implementing BDD packages using Breadth First Search (BFS) With a BFS implementation, the nodes associated with each variable are accessed all together. Therefore, by using one or more pages of memory for each variable, page faults are reduced. The ....

....the BDD package is used such as computing output BDDs or performing reachability analysis. In this paper, we present an in depth analysis of the performance of the memory hierarchy for both BFS and DFS implementations. Our work has been motivated by recent advances in BFS manipulation of BDDs [17] that have made that approach quite competitive. In [17] Sanghavi and co workers compared their package, hereinafter referred to as the CAL package, to David Long s package, hereinafter referred to as the CMU package [13] on a variety of test cases. However, their interpretation of the results ....

[Article contains additional citation context not shown here]

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance BDD package based on exploiting memory hierarchy. In

....Table. The Apply and the If Then Else operator (ITE) are well known representatives of this method. Although ITE gives reasonable results in several applications, recent research has shown that alternative methods might be interesting, e.g. BFS operations [24] and use of memory system hierarchy [26] are often more powerful for very large applications. In [19] a new approach for the implementation of synthesis on BDDs called Multiple OR operation by means of Existential quantification (MORE) was presented. This approach basically realizes an OR operation by the introduction of coding ....

R.K. Ranjan, J.V. Sanghavi, R.K. Brayton, and A. Sangiovanni-Vincentelli. High performance BDD package based on exploiting memory hierarchy. In Design Automation Conf., pages 635--640, 1996.

....size BDD nodes Cluster size BDD nodes Cluster size BDD nodes Figure 4. 5: Time Space tradeoffs in image computation spin offs from BDD based ideas that are proving useful in synthesis and simulation, e.g. 77] Progress on BDD technology and BDD techniques is being made on a regular basis [94]. BDD based approaches to verification do have major shortcomings. For example, there is some evidence that for loosely coupled asynchronous systems, such as cache coherency protocols, careful use of explicit data structures may be superior to BDD based methods [38] This is because constants ....

R. Ranjan, J. Sanghavi, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. High Performance BDD Package Based on Exploiting Memory Hierarchy. In Proc. of the Design Automation Conf., Las Vegas, NV, June 1996.

.... various aspects of circuit testing [9] The success of binary decision diagrams has led to research efforts on a number of fronts, as surveyed in [18] First, there have been many improvements to the core technology, refining the algorithms and representation techniques for improved performance [12, 40, 64, 66]. Secondly, a number of extensions to the data structure have been developed, leading to a more general class of representations known as decision diagrams. Some of these extensions attempt to improve the compactness of representation [7, 28] while The importance and potential impact of these ....

R.K. Ranjan, J.V. Sanghavi, R.K. Brayton, and A. Sangiovanni-Vincentelli, "High performance BDD package based on exploiting memory hierarchy," in Proc. Design Automation Conference (DAC), Las Vegas, NV, June 1996.

....manner, expansions on the parents are scattered in time. The performance impact for the depth first algorithm s poor memory locality is especially severe for BDDs larger than the physical memory. Recently, there has been much interest in BDD construction based on breadth first traversal [16, 17, 2, 11, 20, 7]. In a breadth first traversal, the expansion phase expands operations one variable at a time with all the operations of the same variable expanded together. Furthermore, during the reduction phase, all the new BDD nodes of the same variable are created together. The breadth first construction ....

.... exist in the unique table, 18 insert b into the unique table 19 opNode.result b Figure 6: Reduction Phase of the Partial Breadth First BDD Algorithm To take advantage of structured access in the partial breadth first approach, we associate a specialized BDD node manager for each variable as in [20]. Each variable s BDDnode manager clusters BDD nodes of the same variable by allocating memory in terms of blocks and allocates BDD nodes contiguously within each block. We further extend this concept so that there is one operator node manager for each variable and these node managers are also ....

[Article contains additional citation context not shown here]

Ranjan, R. K., Sanghavi, J. V., Brayton, R. K., and Sangiovanni-Vincentelli, A. High performance BDD package based on exploiting memory hierarchy. In Proceedings of the 33rd ACM/IEEE Design Automation Conference (June 1996), pp. 635--640.

....counterexamples for incorrect implementations. Conventional BDD algorithms [2] are based on depth first traversal of BDD graphs. This approach has small memory overhead, but poor memory locality. To address the issue of constructing large BDDs efficiently, there have been many implementations [14, 15, 1, 10, 18] based on breadth first traversal. The breadth first approach, which exploits its graph traversal pattern by using specialized memory layouts, has better memory access locality and thus often has better performance. However, the breadth first approach can have a large memory overhead, up to ....

....manner, expansions on the parents are scattered in time. The performance impact for the depth first algorithm s poor memory locality is especially severe for BDDs larger than the physical memory. Recently, there has been much interest in BDD construction based on breadth first traversal [14, 15, 1, 10, 18]. In a breadth first traversal, the expansion phase expands operations one variable at a time with all the operations of the same variable expanded together. Furthermore, during the reduction phase, all the new BDD nodes of the same variable are created together. The breadth first construction ....

[Article contains additional citation context not shown here]

R. K. Ranjan, J. V. Sanghavi, R. K. Brayton, and A. SangiovanniVincentelli. High performance BDD package based on exploiting memory hierarchy. In Proceedings of the 33rd ACM/IEEE Design Automation Conference, pages 635--640, June 1996.

....to representation and manipulation. Use of memory hierarchy: If large DDs are considered the graph size often extends the main memory of the computer. Thus, some parts are put to the secondary storage devices. How the paging of the computer can be optimized has been considered in a first study in [34]. Unfortunately, this first approach is not directly compatible with dynamic variable ordering. Reordering based synthesis: As an alternative to the classical recursive synthesis algorithms for DDs a synthesis method based on changing the variable ordering has been presented in [26] for BDDs. ....

R.K. Ranjan, J.V. Sanghavi, R.K. Brayton, and A. Sangiovanni-Vincentelli. High performance BDD package based on exploiting memory hierarchy. In Design Automation Conf., 1996.

....Depth First, Hybrid Approach, Binary Decision Diagram, Formal Verification 1 Introduction Binary Decision Diagrams (BDDs) have been proven successful in representing and manipulating Boolean functions symbolically [5] in a variety of application domains. This success has led to several efforts [3, 13, 14, 1, 11, 10, 15] to provide efficient BDD implementations. Conventional BDD algorithms [3, 11] are based on depth first traversal of the BDD graphs. This approach has the advantage of small memory overhead. Recently, there have been many implementations based on breadth first traversal [13, 14, 1, 10, 15] which ....

....[3, 13, 14, 1, 11, 10, 15] to provide efficient BDD implementations. Conventional BDD algorithms [3, 11] are based on depth first traversal of the BDD graphs. This approach has the advantage of small memory overhead. Recently, there have been many implementations based on breadth first traversal [13, 14, 1, 10, 15], which have found that the breadth first approach has better memory access locality and thus better performance. However, the breadth first approach can have a large memory overhead, especially when the BDDs involved are large. This extra memory overhead can result in an increase of the number of ....

[Article contains additional citation context not shown here]

RANJAN, R. K., SANGHAVI, J. V., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. High performance bdd package based on exploiting memory hierarchy. In Proceedings of the 33rd ACM/IEEE Design Automation Conference (June 1996), pp. 635--640.

....verification by building the BDD [8] representation of two circuits and comparing them. The major underlying computation is memory intensive. We have benchmarked machines for equivalence checking with two kinds of underlying BDD computations random memory access [9] and localized memory access [10]. 3. Logic Synthesis Tool: SIS [11] is a logic synthesis system for combinational and sequential circuits. It takes as input a representation of a set of Boolean functions in the form of a finite state machine or a netlist of gates and latches and provides a set of commands that can be used to ....

....is much higher compared to those in other applications. 3.1.3 VIS This application is highly memory intensive. As mentioned earlier, the underlying data structure (BDDs) can be manipulated with either random or local memory access behavior. We make use of two BDD packages CMU [9] and CAL [10] which have random and local memory access patterns respectively, to get two sets of results. The inputs were taken from MCNC and ISCAS benchmark sets. The performance ratios are shown in Figure 1. In the case of random memory access behavior, we would expect that the memory organization of an ....

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "High Performance BDD Package Based on Exploiting Memory Hierarchy," in Proc. of the Design Automation Conf., (Las Vegas, NV), June 1996.

....crucial for their efficient manipulation. Recently, dynamic ordering [3] has come up as a popular technique to obtain optimal variable orderings. In fact, dynamic ordering is established as a critical component for any BDD package to be used for practical sized problems. Breadth first manipulation [4] techniques preserve the locality of reference and exploit memory hierar 1 In this paper by BDD, we mean Reduced Ordered Binary Decision Diagram. For various terminologies on theory and implementation of a BDD package refer to [1, 2] chy in a computer system to efficiently manipulate very ....

....to both variables x i as well as x i 1 and the index of a node is no longer uniquely identified by its page address. This breaks down the approach given in [6] In addition, arbitrarily overwriting a node destroys their locality. Next we look at the breadth first implementation in CAL [4]. In this approach, a node is represented by an fid, nodeg pair. Also, the node contains the id as well as the address of its cofactor nodes. This data structure avoids the need for cofactor fetching or for looking up any table to determine the cofactor indices. However, like previous ....

[Article contains additional citation context not shown here]

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli, "High Performance BDD Package Based on Exploiting Memory Hierarchy," in Proc. of the Design Automation Conf., June 1996.

....representation is enforced by hash tables known as unique tables. The new subproblems are generally recursively solved in a depthfirst order as in Bryant s original BDD publication [7] Recently, there has been some work that tries to exploit memory locality by using a breadth first order [2, 18, 19, 21, 26]. Before moving on, we first define some terminology. We will refer to the Boolean operations issued by a user of a BDD package as the top level operations to distinguish them from sub operations (subproblems) generated internally by the Shannon expansion process. A BDD node is reachable if it is ....

....NaN F NaN C.E. b) Fig. 7. Effects of the complement edge representation on (a) number of the operations and (b) graph sizes. 4. 4 Memory Locality for Breadth First BDD Construction In recent years, a number of researchers have proposed breadth first BDD construction to exploit memory locality [2, 18, 19, 21, 26]. The basic idea is that for each expansion phase, all sub operations of the same variable are processed together. Similarly, for each reduction phase, all BDD nodes of the same variable are produced together. Note that even though this levelized access pattern is slightly different from the ....

Ranjan, R. K., Sanghavi, J. V., Brayton, R. K., and SangiovanniVincentelli, A. High performance BDD package based on exploiting memory hierarchy. In Proceedings of the 33rd ACM/IEEE Design Automation Conference (June 1996), pp. 635--640.

No context found.

R.K. Ranjan, J.V. Sanghavi, R.K. Brayton, and A. Sangiovanni-Vincentelli, "High performance BDD package based on exploiting memory hierarchy," in Proc. Design Automation Conference (DAC), Las Vegas, NV, June 1996.

No context found.

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance bdd package based on exploiting memory hierarchy. In Proc. of ACM/IEEE Design Automation Conference, 1996.

No context found.

Sanghavi, J. V., R. K. Ranjan, R. K. Brayton and A. Sangiovanni-Vincentelli, High performance bdd package based on exploiting memory hierarchy, in: Proc. of ACM/IEEE Design Automation Conference, 1996.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC