F. Brglez and H. Fujiwara. A Neutral Netlist of 10 Combinational Benchmark Circuits. In IEEE International Symposium on Circuits and Systems, pages 695--698, New Jersey, USA, 1985. IEEE Press. Design  Home/Search Document Not in Database Summary Related Articles Check |
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Coverage-Directed Assignment Approach To BIST - Fiser, Hlavicka, Kubatova (2003) (Correct)
....applies also to the intersections of the coverage sets. 4 Experimental Results ISCAS Benchmarks In order to test the algorithm on some practical examples we have chosen a subset of the ISCAS [10] benchmarks. The test patterns for all benchmark files were generated by the TurboTester [11, 12]. As a pseudorandom pattern generator a LFSR of the width equal to the number of primary inputs of the CUT was used, the number of patterns generated was fixed to 5000. The results are shown in Table 2. For each particular benchmark the number of its primary inputs (r) is given, together with the ....
Brglez, F., Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Minimization of Boolean Functions - Fiser (2002) (Correct)
....(using the generalized column matching method) and thus the better solution can be found. Similarly, the more bits has the PRPG, the more columns we have to choose from and there are more possibilities to find the exact column matches. As an example we have chosen the c432 ISCAS benchmark circuit [Brg85], whose test vectors were generated by an ATPG tool ATOM [ATOM] Test vectors are in their non compressed form, thus they contain don t cares. The c432 circuit has 36 inputs, thus r = 36 and the complete test set contains 520 vectors (s = 520) The C matrix vectors were produced by a LFSR with ....
Brglez, F. - Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Column-Matching Based BIST Design Method - Fiser, Hlavicka (2002) (1 citation) (Correct)
....matches consists in the successive decomposition of both matrices into systems of subsets, until no decomposition is possible. Then some row matching method, e.g. 4] is applied to all the subsets to make the final assignment. To illustrate the method we have chosen the c17 ISCAS benchmark [5] for its simplicity. As input we have a complete test set generated by an ATPG tool. This test set consists of 10 test patterns a j, which are to be assigned to the vectors A J generated by a LFSR with generating polynomial x 5 x 2 1 seeded with the vector 00010. Our goal is to implement a ....
Brglez, F. - Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Using Recursive Decomposition to Construct Elimination.. - Adnan Darwiche And (2001) (Correct)
.... 20.74 munin1 11 10 11 31 12 12 25.19 28.03 munin2 9 13 7 47 9 17 22.16 18.10 munin3 8 16 7 35 10 17 21.84 17.25 munin4 9 13 8 37 10 18 23.75 21.38 pigs 11 11 10 38 14 14 19.02 17.43 water 10 7 10 12 10 9 20.34 20.75 Our first suite of DAGs is obtained from the ISCAS 85 benchmark circuits [2]. These circuits have been studied by El Fattah and Dechter in [8] wherein elimination orders were generated using several well known heuristics. We found that min fill produced better orders than any of the heuristics surveyed in [8] Hence we used min fill to construct elimination orders for ....
F. Beglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN. In Proceedings of the IEEE symposium on Circuits and Systems, 1985. http://www.cbl.ncsu.edu/www/CBL Docs/iscas85.html.
Using Regression Analysis for GA-Based ATPG Parameter.. - Dougherty, Blanton (Correct)
....is inherently a random process, several simulations are required to average results, thereby multiplying the number of experiments. In our work, results were averaged over ten ATPG sessions. Our model building experiments used the ten largest combinational circuits of the ISCAS85 benchmark set [1]. Test generation terminated upon achieving 100 fault coverage, reaching two thousand populations, or observing no progress over three consecutive populations. All of the circuits are known to be testable with at most a few hundred vectors, so experiments of two thousand or more populations ....
F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target simulator in FORTRAN. ISCAS, pp. 695--698, June 1985.
Synthesis Of Mapping Logic For Generating Transformed.. - Touba, McCluskey (1995) (24 citations) (Correct)
....Generator Circuit Under Test x 2 x 3 x 4 Figure 10. Implementation of Mapping Logic for Set of Rectangles in Figure 8 6. EXPERIMENTAL RESULTS The method described in this paper was used to generate mapping logic to reduce the pseudo random pattern test length for some of the ISCAS 85 [Brglez 85] and ISCAS 89 [Brglez89] benchmark circuits that require over a million test patterns. There are three important factors in choosing a test pattern generator for BIST: test time, test quality, and hardware area. To evaluate the test pattern generators that are designed by the method in this ....
Brglez, F., and H. Fujiwara, A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985.
Time and Frequency Domain Transient Signal Analysis.. - Plusquellic.. (Correct)
....the standard device. 4.0 Experimental Design In this section we present the results of several hardware experiments designed to demonstrate that it is possible to characterize ICs using time and frequency domain Signature Waveforms. We designed three versions of the ISCAS85 c432 benchmark circuit [29], a version with intentionally inserted bridging defects, a version with intentionally inserted open drain defects and a defect free version. Four devices of each version were fabricated at MOSIS using ORBIT s 2.0m SCNA process. The defect free devices were verified using both functional and ....
F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN. Special Session on ATPG and Fault Simulation, Int. Symposium on Circuits and Systems, pages 663-698, June 1985.
Defect Detection Using Regression Analysis of.. - Plusquellic.. (Correct)
....one of the most difficult of CMOS defects to detect reliably. The hardware experiments were conducted on three versions of the ISCAS85 c432 benchmark circuit: a version with intentionally inserted bridging defects, a version with intentionally inserted open drain defects and a defect free version [31]. Four devices of each version were fabricated through MOSIS. The four defect free devices and one set of either the open drain or bridging defective devices were used in each experiment. Four experiments were conducted, two bridging experiments labeled Internodal Bridging and Feedback Bridging, ....
F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN. Special Session on ATPG and Fault Simulation, Int. Symposium on Circuits and Systems, pages 663-698, June 1985.
Combining Decision Diagrams and SAT Procedures for.. - Williams, Biere.. (2000) (15 citations) (Correct)
....shifter experiments and a 333 MHz Sun UltraSPARC IIi for the multiplier experiments. 6.1 Multiplier This example comes from the BMC 1.0f distribution 3 . It is a 1616 # 32 shiftand add multiplier. The specification is the c6288 combinational multiplier from the ISCAS 85 benchmark series [7]. For each output bit we verify that we cannot reach a state where the shift and add multiplier has finished its computation and the output bits of the two multipliers di#er. The multiplier fits into the category of SMV programs that we handle well. The operands are not modeled as inputs. Instead ....
F. Brglez and H. Fujiware. A neutral netlist of 10 combinational benchmarks circuits and a target translator in Fortran. In Special Session International Symposium on Circuits and Systems (ISCAS), 1985.
Combining Decision Diagrams and SAT Procedures for.. - Williams, Biere.. (2000) (15 citations) (Correct)
....shifter experiments and a 333 MHz Sun UltraSPARC IIi for the multiplier experiments. 6.1 Multiplier This example comes from the BMC 1.0f distribution 3 . It is a 16 16 32 shiftand add multiplier. The speci cation is the c6288 combinational multiplier from the ISCAS 85 benchmark series [7]. For each output bit we verify that we cannot reach a state where the shift and add multiplier has nished its computation and the output bits of the two multipliers di er. The multiplier ts into the category of SMV programs that we handle well. The operands are not modeled as inputs. Instead ....
F. Brglez and H. Fujiware. A neutral netlist of 10 combinational benchmarks circuits and a target translator in Fortran. In Special Session International Symposium on Circuits and Systems (ISCAS), 1985.
Propositional Theorem Proving by Semantic Tree Trimming for.. - Yakowenko (1999) (Correct)
....strategies. It could therefore be enlightening to consider which problems are handled easily and which are not, bearing in mind the purpose for which each of those was constructed. 5.1. 2 UCSC These problems came from Tracey Larrabee s test pattern generator [39] from problems in ISCAS 85 [8]. They were generated to check for particular kinds of wiring errors: single stuck at faults and bridge faults. These problems have names that begin with ssa and bf , respectively. Larrabee also has a satisfiability checker that solves all of these problems quickly, but it is rather ....
F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN. In Proc. 1985 IEEE Int. Symp. Circuits and Sys., June 1985. Special Session.
Algorithms for Leakage Reduction with - Dual Threshold Design (Correct)
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F. Brglez and H. Fujiwara. A Neutral Netlist of 10 Combinational Benchmark Circuits. In IEEE International Symposium on Circuits and Systems, pages 695--698, New Jersey, USA, 1985. IEEE Press. Design
Postgraduate Study Report DC-PSR-2004-14 - Mixed-Mode Bist Based (Correct)
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F. Brglez and H. Fujiwara. A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Column-Matching BIST Exploiting Test Don't-Cares - Petr Fiser Jan (2003) (Correct)
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Brglez, F. - Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Mixed-Mode Bist Based On Column Matching - Petr Fiser Informatics (2004) (Correct)
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Brglez, F., Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Pseudorandom Testing -- A Study of the Effect of the Generator .. - Petr Fiser Hana (Correct)
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Brglez, F. - Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan. Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Pseudorandom Testability -- Study of the Effect of the - Generator Type Petr (Correct)
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Brglez, F., Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
An Efficient Mixed-Mode Bist Technique - Petr Fiser Hana (2004) (Correct)
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Brglez, F., Fujiwara, H.: A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of International Symposium on Circuits and Systems, pp. 663-698, 1985
Combining Decision Diagrams and SAT Procedures for Ecient.. - Model Checking Poul (2000) (Correct)
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F. Brglez and H. Fujiware. A neutral netlist of 10 combinational benchmarks circuits and a target translator in Fortran. In Special Session International Symposium on Circuits and Systems (ISCAS), 1985.
A Set of Benchmarks for Modular Testing of SOCs - Marinissen (2002) (2 citations) (Correct)
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Franz Brglez and Hideo Fujiwara. A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Simulator in FORTRAN. In Proceedings International Symposium on Circuits and Systems (ISCAS), pages 695-- 698, Kyoto, Japan, May 1985.
Enhanced Clustered Voltage Scaling for Low Power - Monica Donno Luca (Correct)
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F. Brglez, H. Fujiwara, \ A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran" ######### #### ############# ######### ## ######## ### #######, pp.785-794, 1985.
Satisfiability Checking Using Boolean Expression Diagrams - Williams, Andersen, Hulgaard (2000) (Correct)
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F. Brglez and H. Fujiware. A neutral netlist of 10 combinational benchmarks circuits and a target translator in Fortran. In Special Session International Symposium on Circuits and Systems (ISCAS), 1985.
Combining Decision Diagrams and SAT Procedures for - Efficient Symbolic Model (Correct)
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F. Brglez and H. Fujiware. A neutral netlist of 10 combinational benchmarks circuits and a target translator in Fortran. In Special Session International Symposium on Circuits and Systems (ISCAS), 1985.
Diagnosing Realistic Bridging Faults with Single Stuck-at.. - Lavo (1996) (5 citations) (Correct)
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F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran. In Proceedings of the IEEE International Symposium on Circuits and Systems, 1985.
Eliminating Undetectable Shorts between Horizontal Wires.. - McGowen, Ferguson (1994) (Correct)
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F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran. In Proceedings of the IEEE International Symposium on Circuits and Systems, 1985.
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