Jeffrey J. Joyce. More reasons why higher-order logic is a good formalism for specifying and verifying hardware. Technical report 90--35. Department of Computer Science, University of British Columbia, November 1990. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Structuring and Automating Hardware Proofs in a.. - Kumar, Schneider, Kropf (1993) (10 citations) (Correct)
....using the underlying metalanguage ML. The fact that HOL is a public domain, general purpose, interactive theorem proving platform, strengthened by a set of dedicated researchers who constantly strive to bring it to the fore, and furthered by the naturalness of higher order hardware descriptions [18, 19] led to a profusion of activity in this area [20, 21] Large processors at different levels of abstraction [22, 23, 24, 25] and a number of medium sized circuits were formally verified using this approach. Nevertheless, these investigations and other similar attempts using provers like VERITAS ....
J. Joyce. More reasons why higher-order logic is a good formalism for specifying and verifying hardware. In International Workshop on Formal Methods in VLSI Design, Miami,1991.
Embedding Hardware Verification within a Commercial Design .. - Kropf, Kumar, Schneider (Correct)
.... this formalism is usable to describe and verify designs of realistic sizes, e.g. significant parts of the TAMARACK microprocessor have been verified [9] In higher order logic, hardware specifications may be formalized in a natural manner, i.e. comparable to known hardware description languages [8, 10]. Additionally, it is also possible to transform specifications given in a usual HDL like ELLA [11] into a representation in higher order logic [12] For these reasons, the work presented in this paper also relies on the use of higher order logic for specifying and verifying hardware. However, the ....
J. Joyce. More reasons why higher-order logic is a good formalism for specifying and verifying hardware. In International Workshop on Formal Methods in VLSI Design, Miami,1991.
Eliminating Higher-Order Quantifiers to Obtain Decision.. - Schneider, Kumar, Kropf (Correct)
....the presented methods into goals of logics weaker than higher order logic, e.g. temporal) propositional logic. The presented transformations are also capable of dealing with hierarchy and have been implemented in HOL90. 1 Introduction Higher order logic is well suited for hardware verification [Gord86, Joyc91], but unfortunately this logic is neither decidable nor recursively enumerable. Hence, no form of automation is available for the entire logic, although automation is an essential prerequisite for getting verification tools usable by VLSI designers. However, in the limited context of hardware ....
J. Joyce. More reasons why higher-order logic is a good formalism for specifying and verifying hardware. In International Workshop on Formal Methods in VLSI Design, Miami,1991.
A Methodology for Formal Hardware Verification, with Application.. - Beatty (1993) (11 citations) (Correct)
No context found.
Jeffrey J. Joyce. More reasons why higher-order logic is a good formalism for specifying and verifying hardware. Technical report 90--35. Department of Computer Science, University of British Columbia, November 1990.
A Methodology for Formal Hardware Verification, with Application.. - Beatty (1993) (11 citations) (Correct)
No context found.
Jeffrey J. Joyce. More reasons why higher-order logic is a good formalism for specifying and verifying hardware. Proceedings of of the ACM/SIGDA International Workshop in Formal Methods in VLSI Design, January 1991.
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