S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill Companies, Inc. 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the output voltage (Figure 7) During the overshoot the pMOS current is #owing towards VDD as already mentioned. To perform an accurate modelling of the output evolution in this region the subthreshold current of the nMOS device should be taken into account. The subthreshold current is given by [19] I sub = I on e (V GS V TN ) q=nkT ) where I on is the current in strong inversion for V GS =V on and the voltage V on is found as V on =V TN nkT=q where n =1 qN FS =C ox C d =C ox . The SPICE parameter N FS is used as a #tting parameter that determines the slope of the subthreshold ....

....TN ) q=nkT ) where I on is the current in strong inversion for V GS =V on and the voltage V on is found as V on =V TN nkT=q where n =1 qN FS =C ox C d =C ox . The SPICE parameter N FS is used as a #tting parameter that determines the slope of the subthreshold current voltage characteristics [19]. C d is the capacitance associated with the depletion region, q denotes the unit (electron) charge, k is the Boltzmann constant, and T is the temperature. For the purpose of this analysis it is su#cient to approximate the subthreshold current by its #rst order Taylor series approximation around ....

Kang SM, Leblebici Y. CMOS Digital Integrated Circuits: Analysis and Design. McGraw Hill: New York, 1996.

....dynamic circuit requires two identical NMOS evaluation nets. One additional NMOS transistor M3, whose gate voltage is controlled by output signal, provides a conduction path between the common node of evaluation nets and V DD . This technique employs the principle of a Schmitt trigger [9] [10] which can be explained as follows: during the precharge phase, the clock signal F turns M1 on, and output voltage V out is charged to logic high. Assuming that the common node voltage V x is initially discharged, then V x reaches the value V DD V tn . Due to body effect, the switching ....

S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill, 1996.

....(Figure 6) The training points are easily identified as corresponding to the extremes of the distribution relative to the new rotated axis. Design of experiment theory helps to determine the optimal set of training points for the simulations in such a way that the best model is generated [10,11]. The most straightforward way is to perform the simulations with all possible combinations of the extremes of block performances. This approach is called full factorial analysis and requires a full set of 2 n simulations. It is possible to reduce this number. Fractional factorial designs ....

....The main effects (coefficients of A, B, and C) and two factor interaction effects (coefficients of A B, B C, and A C) can still be accurately represented. Only the three factor interaction term is lost but since in most cases such a high order interaction is negligible this loss is permissible [11]. The selection of optimal training points is achieved by considering the uncorrelated variables after the axis are rotated. To find the actual SPICE model file corresponding to a selected point no backward transformation is needed, however. Even though the coordinates were rotated, the ....

S. M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, The McGraw-Hill Companies, Inc., 1996.

.... there is a trade off between high speed and low power dissipation depending on the threshold voltage and the power supply voltage [1] In dynamic storage elements high performance can be compromised when the stored charge at these dynamic circuits gets degraded, due to leakage current [2] 3] [4]. Dynamic circuits, therefore, require refreshing of the stored charge. Care must be taken to refresh these circuits before unacceptable voltage levels occur. On the other hand, circuit refreshing before there is a need to do so leads to an increase in dynamic power dissipation. A predetermined ....

....taken to refresh these circuits before unacceptable voltage levels occur. On the other hand, circuit refreshing before there is a need to do so leads to an increase in dynamic power dissipation. A predetermined frequency at which to carry out the refreshing of dynamic circuits is often used [3] [4]. This frequency is determined by computing the time it takes for the voltage at a dynamic circuit to degrade to the lowest acceptable value. The definition of leakage current I D = I leakage = I S (e VB=nVT Gamma 1) is used as a basis to compute the refreshing frequency [3] Where VB is the ....

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S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits-Analysis and Design. McGraw-Hill, 1996.

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S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design.McGraw-Hill, 2nd ed., 1999.

.... A common technique in high performance chip design is to exploit dynamic logic such as domino CMOS circuits in critical portion of the chip [5] The drawbacks of domino logic are high noise sensitivity due to dynamic node, and incomplete logic family excludes inverting logic such as NAND function [3]. Nevertheless, chip designers need to use domino logic in performance critical path. Low power consumption has been one of the major issues in VLSI design. Supply voltage scaling is an effective technique to reduce power consumption although it can slow down the speed. To compensate for ....

S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill, 2nd ed., 1998.

....architecture so that the power and delay overhead due to the codec circuitry can be compensated by significant savings in switching activities on tightly coupled buses. 2 Interconnect Power Characteristics The average energy consumed by a wire with clock frequency f 1 T clk can be [6] E av lim n n T clk 0 V dd I c t dt n V dd Q av (1) where n is the number of clock cycles observed and I c t represents the drawn current due to transitions in a clock period. Q av is the time averaged charge provided by the power supply to all capacitances of the interconnect and is given ....

S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill, 2nd edition, 1998.

....operating in the saturation region. As the output voltage begins to fall, the transistor switches from saturation into linear operating region. The time required for the output voltage to fall from its initial value to the midpoint voltage level V can be found by using the well known delay model [10], 11] as (7) It can be seen that during the output voltage transition described by (7) the MOS transistor operates in the linear operating mode only for a relatively short amount of time. Consequently, the impact of current degradation in the linear operating region upon the propagation delay ....

....by the input (gate) capacitance of the next stage, it can be shown that the propagation delay times of all inverter stages are identical. The overall propagation delay of the scaled buffer is usually optimized by calculating the scaling factor , for which the propagation delay achieves its minimum [10], 11] 13] The degradation macro model presented in Section II for the simple CMOS inverter circuit can now be applied to the scaled inverter chain structure. To accomplish this, the two design parameters identified earlier as being representative for the degradation of the CMOS inverter, ....

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S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits ---Analysis and Design. New York: McGraw-Hill, 1996.

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S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill Companies, Inc. 1996.

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S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill Companies, Inc. 1996.

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S. M. Kang and Y Leblebici. CMOS Digital Integrated Circuits Analysis and Design, McGraw-Hill Companies, Inc., page 124.

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S. M. Kang and Y Leblebici. CMOS Digital Integrated Circuits Analysis and Design, McGraw-Hill Companies, Inc., page 68.

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S. Kang, Y. Leblebici, "CMOS Digital Integrated Circuits, Analysis and Design," McGraw-Hill, 1999.

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S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill: New York, 1995.

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S-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, New York: McGraw-Hill, 1996.

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S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill: New York, 1995.

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