Rupp, C., Landguth, M., Garverick, et al., "The NAPA Adaptive Processing Architecture",  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and that the granularity of transaction between hardware and software is both large and deterministic (so that operations can be scheduled) with minimal synchronization between the two. Recently, hybrid Configurable System on a Chip (CSOC) architectures, proposed several years ago ( 12] 7] [13]) have begun to appear as commercial offerings ( 1] 18] In contrast to traditional FPGAs, these integrated systems offer a processor and an array of configurable logic cells on a single chip. On such systems, it becomes feasible to have software and hardware communicate at clock cycle latency ....

C. Rupp et al. The Napa Adaptive Processing Architecture. FCCM 1998.

....are connected as a co processor on the I O bus of a standard microprocessor. While appropriate for coarse grained problems, the disadvantage of these board based systems is that they have high communication latencies and configurable hardware cost. Medium grained architectures include NAPA [10]. In NAPA, the Adaptive Logic Processor (ALP) can access the same memory space as the Fixed Instruction Processor (FIP) so the communication overhead between the ALP and the FIP is reduced compared with the coarse grained architectures, but this approach still does not give the ALP full access to ....

C. R. Rupp and M. Landguth et al. The NAPA Adaptive Processing Architecture. Proceedings IEEE Symp. on FPGAs for Custom Computing Machines. Napa Valley, CA, USA 15-17, April 1998

....arithmetic. In order to give a short overview about similar projects on configurable computing, we recall 1) the Cameron Project (http: www.cs. colostate.edu cameron) in which a framework to automatically compile C programs onto programmable devices was developed, 2) the NAPA architecture [1] with the NAPA C compiler [2] which allows the partitioning of applications between fixed instruction processors and configurable coprocessors, 3) the DEFACTO project (see www.isi.edu asd defacto ) in which, starting from C or MATLAB specifications and using the SUIF compiler ....

....= 1 1 0 1 0 , i.e. data produced at time t by processor p will be used at time (t 1) d t =1) by processor (p 1) d p =1) Finally, the VHDL source, which contains nearly 5000 lines of code, was automatically produced. Ind [i,j] Par[n,m] m =1,n =1 ; String sequence Input p[1] 0 =i =n 1 ; Peptide sequence Input s[1] 0 =i =m 1 ; Output sequence Result M; Equation 1 M[ InitMatch( m 1 =i =n 1,j= 1 ; Equation 2 M[ PropagateMatch( i j = 1,j =0,i = m 1 ; Equation 3 M[ AddMatch(p[i j] s[j] M[i,j 1] 0 =i j =n 1,0 =j =m 1 ; ....

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C.R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J.M. Arnold, and M. Gokhale: 'The NAPA Adaptive Processing Architecture', Proc. IEEE Symp. on FPGAs for Custom Computing Machines, 1998

.... [68, 81, 151, 152] Hybrid ar chitectures have been targeted at accelerating applications such as symmetric key cryp tography, digital signal processing, data compression, image processing, video processing, multimedia, block matching, automated target recognition, and wireless communications [9, 20, 21, 30, 35, 68, 69, 73, 81, 116, 120, 123, 134, 153]. Examples of hybrid architectures include A7, Chimaera, ConCISe, DREAM, ES, Garp, MorphoSys, NAPA, OneChip, PRISC, and ReRISC. A7 and E5 The Triscend A7 32 bit configurable system on chip consists of an ARM7TDMI processor core combined with a Configurable System Logic (CSL) programmable matrix. ....

....and both may access the same memory space. While the ALP has general access to the RISC processor s memory space, high speed memories are dedicated to the ALP to improve performance. The ALP may be partially reconfigured, resulting in a wide range of functions being available to the RISC processor [27, 120]. OneChip The OneChip architecture encompasses a MIPS like processor that is tightly coupled to reconfigurable logic termed the programmable functional units (PFUs) OneChip may be configured to not make use of the PFUs so as to maintain binary compatibility with standard MIPS applications. The ....

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C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. M. Arnold, and M. Gokhale. The NAPA Adaptive Processing Architecture. In Sixth Annual IEEE Symposium on Field-Programmable Uustom Uomputing Machines, FUUM '98, pages 28-37, Napa Valley, California, USA, April 15-17 1998. IEEE, Inc.

....we do, that partitioning should be done at procedure interfaces. In his proposal the RH is still relegated to a slave role, as it cannot invoke services on the CPU, and can implement only leaf functions of the call graph. # Another class of coarse grain reconfigurable systems consists of NAPA1000 [15], RAW [21] Smart Memories [12] All these systems are more related to multiprocessors than to a simple CPU RH model. In these systems the interface between the multiple computational units is highly specialized; it is not clear how much these systems would benefit from the use of a procedural ....

C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale. The NAPA adaptive processing architecture. In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '98), April 1998.

....design of the system. More concepts involved in run time reconfiguration (the dynamic reconfiguration of devices during computation execution) are discussed in a later section. The actual execution model of the reconfigurable hardware varies from system to system. For example, the NAPA system [Rupp98] by default suspends the execution of the host processor during execution on the reconfigurable hardware. However, simultaneous computation can occur with the use of fork and join primitives, similar to multiprocessor programming. REMARC [Miyamori98] is a reconfigurable system that uses a ....

....environment with the addition of custom instructions that may change over time. Here, the reconfigurable units execute as functional units on the main microprocessor datapath, with registers used to hold the input and output operands. Second, a reconfigurable unit may be used as a coprocessor [Wittig96, Hauser97, Miyamori98, Rupp98, Chameleon00]. A coprocessor is in general larger than a functional unit, and is able to perform computations without the constant supervision of the host processor. Instead, the processor initializes the reconfigurable hardware and either sends the necessary data to the logic, or provides information on where ....

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C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. M. Arnold, M. Gokhale, "The NAPA Adaptive Processing Architecture", IEEE Symposium on Field-Programmable Custom Computing Machines, 1998.

....term OneChip from now on to refer to the latest version of the OneChip architecture. 1. 1 Related Work In general, a system that combines a general purpose processor with reconfigurable logic is known as a FieldProgrammable Custom Computing Machine (FCCM) Research on FCCMs done by other groups [2, 5, 7, 14, 16, 18, 19] has reported speedup obtained by combining these two techniques, however, most of the research in these groups is focused on aspects of the reconfigurable fabric and the compilation system. Much of the OneChip work is focused toward the interface between the two technologies. As a result, the ....

....no standard application benchmarks available for reconfigurable processors. However, other groups have reported performance improvement results similar to the ones presented in this paper, using Mediabench and SPEC benchmarks [2, 23] Although Onechip shares certain similarities with other systems [2, 19] that target memory streaming applications and focus on loop level code optimizations, a standardized set of benchmarks and metrics for reconfigurable processors is needed to properly evaluate the di#erences between them. 8. ACKNOWLEDGEMENTS We would like to akcnowlegde Chameleon Systems Inc. for ....

C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. A. Arnold, and M. Gokhale. The NAPA adaptive processing architecture. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 28--37, Apr. 1998.

....an embedded microcontroller, a block of SRAM, a system bus and configurable logic interconnected inside a single chip. The configurable logic may be used through the circuit generator modules included in a library. NATIONAL SEMICONDUCTOR The National Adaptive Processing Architecture (NAPA) [44] combines an adaptive logic processor with a fixed instruction processor, memory and an interconnection network interface. The Napa C compiler [19] is an assisted compiler that requires user intervention to explicitly target the desired fabric. ANNAPOLIS The Annapolis Wildfire family [45] are ....

Rupp, C. R., M. Languth, T. Garverick, E. Gomersall, H. Holt, J. M. Arnold and M. Gokhale. "The NAPA Adaptive Processing Architecture", Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'98), April 1998, pp. 28-37.

.... this model is only effective if the computation to communication ratio is high (for instance, for specialized bit level functions which are not supported by standard microprocessors [5] or for closely coupled systems which combine reconfigurable hardware and a processor kernel on the same chip [6, 7] and thus have a much smaller communication overhead. Furthermore, the semantics of the sequential input program constrains the execution order of software instructions, hardware coprocessors, and the data transfers. Only fine grain parallelism is possible if local analyses detect independent ....

C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall and H. Holt. The NAPA adaptive processing architecture. In Proc. FPGAs for Custom Computing Machines. IEEE Computer Society Press, 1998.

....MIPS core. 2.3. 4 National Adaptive Processing Architecture (NAPA) National Adaptive Processor Architecture (NAPA) is part of the Adaptive System on a Chip (ASC) series which is aimed at providing a integrated hardwired standard and application specific softwired programmable functional blocks [66]. It is targeted towards DSP applications, Imaging, Feature Extraction problems, Encryption Decryption etc. 30 NAPA 1000 is a high performance, low power Adaptive Processing Architecture from National Semiconductor. The device consists of a 32 bit RISC processor core and a 50K gate Adaptive Logic ....

....and the associated software tools for mapping onto their specific architecture. Some of these projects have addressed generic mapping techniques that can be extended to a class of reconfigurable architectures. Such projects include the Berkeley Garp [75, 21, 41] National Semiconductor NAPA [36, 66], Xputer [44] Northwestern MATCH [6] MIT RAW [77] CMU PipeRench [38] DEC PeRLe [76] SPLASH [19] The Garp and NAPA projects address some of the issues in mapping loops onto reconfigurable architectures. However, they are heavily based on loop analysis and do not develop a model based mapping ....

[Article contains additional citation context not shown here]

C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale. The NAPA Adaptive Processing Architecture. In IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.

....and that the granularity of transaction between hardware and software is both large and deterministic (so that operations can be scheduled) with minimal synchronization between the two. Recently, hybrid Con gurable System on a Chip (CSOC) architectures, proposed several years ago ( 8] 5] [9]) have begun to appear as commercial o erings ( 1] 10] In contrast to traditional FPGAs, these integrated systems o er a processor and an array of con gurable logic cells on a single chip. On such systems, it becomes feasible to have software and hardware communicate at clock cycle latency ....

C. Rupp et al. The Napa Adaptive Processing Architecture. FCCM 1998, Apr. 1998.

....of this architecture model is the NAPA 1. This project is supported by Defence Advanced Research Projects Agency (DARPA) under the Adaptive Computing Systems (ACS) program. Reconfigurable FPGA Coprocessor Memory CPU I O Figure 1. Reconfigurable ACS An Architecture Model adaptive processor [1]. This ACS architecture model is useful in that it effectively implements most of the target ACS applications. This is because it not only preserves the benefits of the traditional Von Neumann programmable memory model but also augments it with a programmable reconfigurable FPGA coprocessor. ....

....without significantly sacrificing the performance of applications. In the event of scarcity of resources, reconfiguration can be used to enable graceful degradation. Instead of implementing our proposed dependable ACS model in an actual chip implementation, like the NAPA Adaptive processor [1], we will use the Quickturn emulation platform. Quickturn emulation platform will allow us the flexibility to evaluate variants of the dependable ACS model for the target applications. In addition to the emulation system support, Quickturn design systems will contribute in instrumenting rapid ....

C. R. Rupp, M Landguth, T. Garverick, E. Gomersall, H. Holt, J. M. Arnold, and M. Gokhale, "The NAPA Adaptive Processing Architecture," Proc. IEEE Symp. FCCM'98, Apr. 1998.

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C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale, "The Napa Adaptive Processing Architecture," in IEEE Symposium on FPGAs for Custom Computing Machines, K. L. Pocek and J. Arnold, eds., pp. 28--37, IEEE Computer Society Press, 1998.

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Rupp, C., Landguth, M., Garverick, et al., "The NAPA Adaptive Processing Architecture",

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C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. M. Arnold, and M. Gokhale, The NAPA Adaptive Processing Architecture, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, pp. 28--37, (1998).

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Rupp C. et al., "The NAPA Adaptive Processing Architecture", Proc. of the IEEE Symp. on FPGAs for Custom Computing Machines (FCCM), Napa (CA, USA), 1998 2.9 92

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C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale, "The NAPA adaptive processing architecture," in IEEE Symp. Field-Programmable Custom Comput. Machines, Napa, CA, Apr. 1998, pp. 23--37.

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C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale, "The NAPA adaptive processing architecture," in IEEE Symp. Field-Programmable Custom Comput. Machines, Napa, CA, Apr. 1998, pp. 23--37.

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C.R. Rupp et al., \The NAPA Adaptive Processing Architecture, " in Proc. IEEE Symp. on FPGAs for Custom Computing Machines, Napa Valley, California, 1998, pp. 28-37.

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C. Rupp et al. The NAPA Adaptive Processing Architecture. In Proc. 6th IEEE Symp. on FCCMs, pp. 28-37, Napa Valley, California, 1998.

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C. Rupp et al. The NAPA Adaptive Processing Architecture. In Proc. 6th IEEE Symp. on FCCMs, pp. 28-37, Napa Valley, California, 1998.

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C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale. The NAPA Adaptive Processing Architecture. In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '98), April 1998.

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C. Rupp et. al., "The NAPA Adaptive Processing Architecture", IEEE Symposium on FieldProgrammable Custom Computing Machines, Napa, California, April, 1998.

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C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. M. Arnold, and M. Gokhale, "The NAPA adaptive processing architecture," in Proc. IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'98), pp. 28--37, 1998.

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C.R. Rupp, M Landguth, T. Garverick, E. Gomersall, H. Holt, J.M. Arnold, and M. Gokhale, "The NAPA Adaptive Processing Architecture," Proc. IEEE Symp. Field-Programmable Custom Computing Machines, Apr. 1998.

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