D. Thomas, J. Adams, and H. Schmitt, "A Model and Methodology for Hardware -Software Codesign," IEEE Design & Test of Computers, Vol. 10, No. 3, pp. 615, 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and refinement of the communication units, SOLAR is best suited for communication driven design processes. SOLAR is the underlying model of the COSMOS design environment [Ism94] Interacting Processes. This model consists of independent interacting sequential processes derived from CSP [Tho93]. The communication is performed through channels but, unlike CSP, 17 there exist additional primitives that permit unbuffered transfer and synchronization without data. 3.1.4 DISCRETE EVENT A Discrete Event (DE) system can be defined as a discrete state event driven system. In other words, its ....

D. E. Thomas, J. K. Adams, and H. Schmit, "A Model and Methodology for Hardware-Software Codesign," in IEEE Design & Test of Computers, vol. 10, pp. 615, Sept. 1993.

....methodologies to prototype such systems, viewing the time to market reduction. In general, embedded systems are built with hardware and software parts developed concomitantly, a method usually named codesign. Coware N2C [1] Ptolemy [2] SEA [4] VCC [5] Seamless [6] and the work described in [7] are typical environments supporting codesign. These environments start from a system level specification with languages like SDL (Specification and Description Language) 8] Esterel [3] Java and C C extensions. A typical codesign flow starts with an informal specification of the whole ....

D. E. Thomas, J. K. Adams and H. Schmit . A model and methodology for Hardware-Software Codesign. IEEEDTC, vol. 10(3), pp. 16-28. 1993.

.... systems by synthesizing and simulating processors [25] Rowson and Sangiovanni Vincentelli designed an event based simulator that sacrifices superfluous details to improve simulation speed [26] 26] Thomas et al. used separate Unix processes to simulate hardware and software described in Verilog [27]. Researchers have worked on automating the communication oriented portions of embedded system design. Castelluccia et al. developed software to automatically compile efficient protocol code from an abstract specification [28] Freund et al. automated the assignment, bus scheduling, and protocol ....

D. E. Thomas, J. K. Adams, and H. Schmit, "A model and methodology for hardware-software codesign," IEEE Design and Test of Computers, vol. 10, no. 3, pp. 6--15, 1993.

.... 96 0 89791 848 7 96 4.00 1996 IEEE components that realise an efficient implementation, typically optimised for price performance. Normally these approaches are targeted towards a fixed implementation environment that has a pre defined operating system, processor and support hardware, e.g.[4, 5, 6]. Other methods for the engineering of computer based products have been proposed that consider the complete process. These include the initial specification of the operating behaviour of the product and its transformation into a hybrid implementation that includes applicationspecific software ....

D. E. Thomas, J. K. Adams and H. Schmit, "A Model and Methodology for Hardware-Software Codesign" IEEE Design and Test of Computers, Vol. 10, No. 3, pp 6-15, 1993

....to complement performance or add functionality not achievable by pure program implementations. Recent advances in hardware synthesis and the proliferation of advanced and inexpensive microprocessors and processor cores have lead to the emergence of research interests in hardware software co design [4, 5,6,7,8,9,10]. Synthesis of systems containing re programmable components can be thought of as extension of highlevel synthesis techniques to systems containing generalized resources . However, due to differences in the computation model of the operations implemented in re programmable and ....

D. E. Thomas, J. K. Adams, and H. Schmit, "A model and methodology for hardware-software codesign," IEEE Design & Test of Computers, pp. 6-15, Sept. 1993.

....keyboard mouse device, and we show that the hardware software synthesis system can be made robust with respect to small changes in the specification. 1 Introduction Several approaches to co design of reactive real time digital systems from behavioral specifications have been proposed in the past [7, 6, 15, 3, 2, 5, 16]. In particular, we consider a design flow as shown in Figure 1. The major weakness of such systems is their inability to handle specification changes. During the life cycle of a digital system, some of its components often need to be redesigned. Redesign addresses the problem of updating an ....

D. E. Thomas, J. K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design & Test of Computers, pages (15, September 1993.

.... do not explore techniques for fine grain cosynthesis [21] including synthesis of applicationspecific instruction processors (ASIPs) 43] nor do we explore cosynthesis for control dominant systems, such as those based on procedural language specifications [22] communicating sequential processes [50], and finite state machine models [6] All of these are important directions within cosynthesis research, but they do not fit centrally within the DSP oriented scope of this chapter. Motivation for coarse grain dataflow specification stems from the growing trend towards specifying, analyzing, and ....

D. E. Thomas, J. K. Adams, and H. Schmitt, "A Model and Methodology for Hardware/Software Codesign," IEEE Design and Test of Computers Magazine, vol. 10, pp. 6--15, 1993.

....research has been done [10] but more is still needed to solve these problems. There is also a need for the next level of research involving partitioningthe system level description into hardware and software as well. There are many ways of approaching this research and many tradeoffs to consider [9] [2] 11] 5] 1.1. Motivation Figure 1 illustrates a typical top down design process. First, a conceptual system definition of the product is created. This definition can be graphical, textual, symbolic or any combination of these methods. Next, the definition is converted into a system ....

....partitions are compiled and the object code is simulated with an RTL (register transfer level) simulator. The hardware estimations are performed by synthesizing the hardware partitions and also feeding the results into the RTL simulator. The hardware software codesign environment created by [9] uses Verilog for the hardware description and C for the software description. The input into their codesign tool consists of a complete functional description of the system, a technology description and performance goals. Partitioning the input system is done by breaking it up into nontrivial ....

D. E. Thomas, J. K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, pages 6--15, September 1993.

....when using a cycle based hardware simulator. Our approach is different from those described e.g. in [9, 13, 14] that rely on a single custom simulator for hardware and software, because we can use any commercial VHDL simulator. It is also different from the class of solutions described e.g. in [11, 19, 20, 6, 21] that execute the software and hardware partitions in separate processes, keeping track of time independently in the two domains, because it does not require elaborate mechanisms to synchronize them. In particular, we do not need a cycle accurate nor a bus cycle model of the target processor. Only ....

D.E. Thomas, J.K. Adams, H. Schmit "A Model and Methodology for Hardware-Software Codesign" IEEE Design and Test of Computers, vol. 10(3):6-15, Sept. 1993.

.... communication cost Barros (1) 100] Unity (HDL) operation similarity clustering concurruency sequencing Barros (2) 101] Occam operation similarity clustering hierarchy concurrenency sequencing hierarchy Kalavade [102] acyclic DFG operation schedulability heuristic with look ahead Adams [103] HDL ( task profiling (SW) hand synthesis (HW) Eles [104] VHDL task profiling simulated annealing Luk [105] Ruby (HDL) operation rate matching hand hierarchy Steinhausen [106] CDFG (HDL, C) operation profiling hand Ben Ismail [107] communicating task hand processes Antoniazzi [108] ....

J.K. Adams, H. Schmitt, and D.E. Thomas, "A model and methodology for hardware-software codesign," in Proc. of the Int. Workshop on Hardware-Software Codesign, Oct. 1993.

....of a commercial hardware simulator. In this approach, the simulator and software compiled on the host processor interact via a bus cycle emulator inside the hardware simulator. The software and hardware simulator execute in separate processes and the two communicate via UNIX pipes. Thomas et al. [59] take a similar approach. Another approach keeps track of time in software and hardware independently, using various mechanisms to synchronize them periodically. For example, ten Hagen et al. 60] describe a two level co simulation environment that combines a timed and untimed level. The untimed ....

....TABLE II A COMPARISON OF CO SIMULATION METHODS. Author Hardware Simulation Software Simulation Synchronization Mechanism Gupta [56] logic custom bus cycle custom single simulation Rowson [57] logic commercial host compiled handshake Wilson [58] logic commercial host compiled handshake Thomas [59] logic commercial host compiled handshake ten Hagen (1) 60] logic commercial host compiled handshake ten Hagen (2) 60] cycle based cycle counting tagged messages Kalavade (1) 61] logic custom host compiled single simulation Kalavade (2) 61] logic custom ISA single simulation Lee [61] ....

D.E. Thomas, J.K. Adams, and H. Schmitt, "A model and methodology for hardware-software codesign," IEEE Design and Test of Computers, vol. 10, no. 3, pp. 6--15, Sept. 1993.

....a hardware description language, e.g. VHDL or Verilog, as a starting point for codesign. Initially, everything can be assumed to be implemented in hardware. Afterwards, some parts of the functionality can be moved to software. There are numerous examples of this method available in the literature [26, 36, 52, 55]. In codesign, one can also start from a neutral graphical description, like MOOSE [44] However, it is also possible to start from a software oriented language, like C C , and later move some parts from software to hardware [20, 45] In our work we start from an abstract high level ....

D. E. Thomas, J. K. Adams, H. Schmit. A Model and Methodology for HardwareSoftware Codesign, IEEE Design & Test of Computers, Vol. 10 (1993), No. 3, pp. 6-15.

....using Cadence Verilog XL simulator and Unix socket. They used C and Verilog in describing the software and the hardware components, respectively. Their cosimulation is a combination of synchronized handshake and cycle accurate processor model. Thomas, Adams, and Schmit s cosimulation scheme [3] is similar to [2] but their technique is based on synchronized handshake with no processor model. Cosimulation techniques of Poseidon [4] and Ptolemy [5] need pin level model of processors. Their approaches are most accurate but take much more simulation time. In this paper, we present a ....

D. E. Thomas, J. K. Adams, and H. Schmit, "A model and methodology for hardware-software codesign," IEEE Design and Test of Computers, pp. 6-15, September 1993.

....of the time constraints and cost, the generation of executable code, the synthesis of hardware, and the production of the interface between hardware and software, i.e cosynthesis. A lot of work has been done, the purpose of which was to define a well structured methodology for codesign [7] 11] [19]. An important point was generally the description of both hardware and software using the same language, like for instance Vhdl enhanced with mechanisms for calling C functions [14] or high level languages like C, C or Fortran extended with facilities for the description of hardware systems ....

Thomas D.E., Adams J.K., Schmit H.: "A Model and Methodology for HardwareSoftware Codesign" IEEE Design & Test of Computers, September 1993, 10, (3), pp. 6-15

....unit on a distributed network using UNIX socket. They used C and Verilog in describing the software component and the hardware component, respectively. Their cosimulation is a combination of synchronized handshake and cycle accurate processor model. Cosimulation scheme of Thomas, et al. [18] is similar to [5] but their technique is based on synchronized handshake with no processor model. Cosimulation techniques of Poseidon [7] and Ptolemy [8] need pin level model of processors. Their approaches are most accurate but take much more simulation time. Although above existing approaches ....

D. E. Thomas, J. K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, pages 6--15, September 1993.

....in the hardware components were modified. These parts were connected through simulator extension constructed using programming language interface (PLI) of Verilog HDL. They developed hardware and software of NIU between HIPPI link and PXPL5 ring network using this technique. l Thomas, et al. [5] implemented a cosimulation environment using Unix socket and Verilog hardware simulator and PLI in a manner similar to Becker, et al. They hid system details such as processor architecture and bus interface by abstraction and simplified interactions among system components as transactions among ....

D. E. Thomas, J. K. Adams, and H. Schmit, " A model and methodology for hardware-software codesign," IEEE Design and Test of Computers, pp. 6-15, September 1993.

....electronic fuel injection, portable CD players or palm top computers. Stringent processing and reliability requirements imposed on these complex systems as well as the need for low cost and little time to market make a revision of the traditional design methods necessary. A number of authors [2,3,7,8,13] have been suggesting various approaches to address these issues using hardware software codesign. We have been proposing a high level system design approach called model based codesign that relies heavily on simulation modeling techniques to explore the feasibility of virtual prototypes [1,12] ....

....implementation for the verified model. 3. Model Mapping Model mapping is preceded by an extensive modeling, refinement and simulation phases [12] To obtain a simulatable specification, we use the Discrete Event System Specification formalism (DEVS) The DEVS formalism introduced by Zeigler [13] provides a means of specifying a mathematical object called a system and supports building models in a hierarchical, modular manner. We arrive at a final verified model after an iterative modeling and simulation loop performed in DEVS Java, an object oriented implementation of DEVS. The product ....

D.E. Thomas, J.K. Adams, and H. Schmit, "A Model and Methodology for Hardware-Software Codesign", IEEE Design and Test of Computers, 10(3), pp. 6-15, 1993.

....2 and several figures from Figure 3 through Figure 6. 3.1 Codesign Methodologies 3.1.1 Four Typical Methodologies Papers No. 1, 3, 4, and 8 presented the most comprehensive work which could be classified into four typical categories of codesign methodology. 1. CSP Based Methodology Paper No.1[2] presents a behavioural model of a class of mixed hardware software systems and defines a codesign methodology for such systems. The methodology includes hardware partitioning, behavioural synthesis, software compilation, and examination on a testbed consisting of a commercial CPU, ....

....Hardware C as an extension of system synthesis could be replaced by the more powerful ones, which would bring about higher level system description. 6 No. Author Title Main Topic 1 Donald E. Thomas et al. Carnegie Mellon University ) A model and Methodology for Hardware Software Codesign[2] A methodology with mixed system model that facilitates cosynthesis and cosimulation 2 Asawaree Kalavade et al. University of California, Berkeley ) A Hardware Software Codesign Methodology for DSP Application[3] A codesign methodology applicable to digital signal processing and ....

Donald E. Thomas, Jay K. Adams, and Herman Schmit, "A Model and Methodology for HardwareSoftware Codesign", in IEEE Design & Test of Computers, Vol. 10, No. 3, September 1993, pp. 6-15.

.... extensive comparison of synchronous languages the reader may refer to [9] Hardware software partitioning issues have not been considered so far, nevertheless our approach is also related to software hardware co design [20] environments for embedded system such as Polis [2] VULCAN [21] COSYMA [7], Chinook [5] etc. The closest to our approach is Polis. Others systems are either based on variations of the C language or on HDL language. Compared Irisa A Synchronous Approach for Hardware Design 31 to Polis, rather than having multiple front ends to a finite state machine language, our ....

D.E.Thomas, J.K.Adams, and H.Schmitt. A Model and Methodology for Hardware-Software Codesign. IEEE Design & Test of Computers, pages 6--15, September 1993.

....bus transactions. Translation based models 29 paper hardware software synchronization simul. simul. mechanism Gupta [GJM92] logic custom bus cycle custom single simul. Rowson [Row94] logic commercial host compiled handshake Wilson [Wil94] logic commercial host compiled handshake Thomas [TAS93] logic commercial host compiled handshake ten Hagen (1) tHM93] logic commercial host compiled handshake ten Hagen (2) tHM93] cycle based cycle counting tagged messages Kalavade (1) KL92] logic custom host compiled single simul. Kalavade (2) KL92] logic custom ISA single simul. Lee [KL92] ....

....of a commercial hardware simulator. In this approach, the simulator and software compiled on the host processor interact via a bus cycle emulator inside the hardware simulator. The software and hardware simulator execute in separate processes and the two communicate via UNIX pipes. Thomas et al. TAS93] take a similar approach. Another approach keeps track of time in software and hardware independently, using various mechanisms to synchronize them periodically. For example, ten Hagen et al. tHM93] describe a two level co simulation environment that combines a timed and untimed level. The ....

D.E. Thomas, J.K. Adams, and H. Schmitt. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, 10(3):6--15, September 1993. 65

....communication cost Prog. Barros (1) BRX93] Unity (HDL) operation similarity clustering concurr. sequenc. Barros (2) BS94] Occam operation similarity clustering hierarchy concurr. sequenc. hierarchy Kalavade [KL94] acyclic DFG operation schedulability heuristic with look ahead Adams [AST93] HDL ( task profiling (SW) hand synthesis (HW) Eles [EPD94] VHDL task profiling sim. anneal. Luk [LW94] Ruby (HDL) operation rate matching hand hierarchy Steinhausen [SCG 93] CDFG (HDL, C) operation profiling hand Ben Ismail [IAJ94] communicating task hand processes Antoniazzi ....

J.K. Adams, H. Schmitt, and D.E. Thomas. A model and methodology for hardware-software codesign. In Proceedings of the International Workshop on Hardware-Software Codesign, October 1993.

....Project ARIES The hardware and software components of embedded systems are highly interrelated. In order to effectively consider the trade offs in embedded system design, the hardware and software should be designed and evaluated in a unified environment. Hardware software co design methodologies [21, 30, 53, 40, 10] have evolved to support concurrent and unified development of the hardware and software components. This section begins with a high level description of hardware software co design. 35 Partitioning Hardware Software System Evaluation Hardware Software Co Simulation Hardware Synthesis ....

D. Thomas, J. Adams, and H. Schmit. A model and methodology for hardwaresoftware codesign. IEEE Design & Test of Computers, pages 6--15, September 1993.

....issue in hardware synthesis from operation centric descriptions. 1. 2 Comparison to Other High level Frameworks Behavioral descriptions typically describe hardware, or hardware software systems, as multiple threads of computation that communicate via a message passing or shared memory paradigm [13, 4, 14, 17, 5]. As in CFSM frameworks, designers of behavioral descriptions still need to manage the interactions between concurrent computations explicitly. In reconfigurable computing, both sequential and parallel programming paradigms have been used to capture functionalities for hardware implementation. ....

D. E. Thomas, J. K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, September 1993.

....destination, increasing the delay, and using up valuable FPGA I Os. However, whether the routing flexibility of the two level topology justifies the substantial cost of the FPICs is unclear. Other two level systems have been constructed with a variety of topologies between the routing only chips [Adams93, Galloway94, Njlstad94] A B C D E F G H R External Interface External Interface RAM RAM RAM RAM RAM RAM RAM RAM Figure 15. The Splash 2 topology [Arnold92] The linear array of FPGAs (A H) is augmented by a routing only crossbar (R) Note that the real topology has 16 FPGAs in the ....

....better than a purely FPGA based solution. There have been several systems that have used crossbar chips or FPICs in crossbar [Kadi94, Weiss94] and hierarchical crossbar topologies [Varghese93] as well as hybrid crossbar linear array topologies [Arnold92, Darnauer94, Carrera95] and other systems [Adams93, Aptix93b, Casselman93, Galloway94, Njlstad94, Herpel95, Hgl95, Van den Bout95] A D E B C F Host Interface Figure 22. The MORRPH topology [Drayer95] Sockets next to the FPGAs allow arbitrary devices to be added to the array. Buses connected to external connectors allow multiple boards to ....

J. K. Adams, H. Schmitt, D. E. Thomas, "A Model and Methodology for Hardware-Software Codesign", International Workshop on Hardware-Software Codesign, 1993.

....cosimulation and the interlanguage communication synthesis. Cosimulation is currently very popular for electronic system design. Several existing works provide methodologies for hardware software cosimulation at the RTL and behavioral level. Coware [14] Seamless [8] and the work described in [15] are typical environments supporting such a co design scheme. Few systems in the literature tried to tackle the multilanguage co design at the systemlevel. These are RAPID [13] Ptolemy [10] and SEA [9] However very little work was done in the field of the refinement of communication between ....

D.E. Thomas and J.K. Adams and H. Schmit, "A model and methodology for Hardware-Software Codesign", IEEEDTC, 10(3), (Sept.), 1993, pp. 16-28.

....main Codesign steps in this case are interlanguage communication synthesis and subsyste refinements [16] Most of existing tools in this area provides few refinements and they start the design at quite a low level e.g. RTL for Hardware and C language for Software. Coware [22] Seamless [9] and [24] are typical environments supporting such a codesign scheme. They start from a mixed description given in VHDL or VERILOG for hardware and C for software. All of them allow for cosimulation. However, only Coware allows for interface synthesis [2] Only few systems in the literature tried to ....

D.E. Thomas and J.K. Adams and H. Schmit. 1993 (Sep.). A Model and Methodology for Hardware-Software Codesign. IEEEDTC, 10(3), pages 16-28.

....systems. Software constraint analysis. 1 Introduction Driven by the proliferation of powerful general purpose microprocessors in recent years there has been a surge of interest in digital system implementations that use these processors as another component along with memory and logic chips [1, 2, 3, 4, 5]. The primary motivation for using predesigned processors is to reduce the design time and cost of design by implementing functionality using a program on the processor. However, a purely software implementation often fails to meet required timing performance for embedded systems. Therefore, ....

....see text. Table 2: Variable types and alignment used Example 2.1. Variable storage assignments. The following shows the set of variables used in the definition of a flow graph and the corresponding storage assignments in the software implementation of the graph (as generated by Vulcan) a[1], b[2] c[3] d[4] e[5] structf a:1; b:2; c:3; d:4; f:5 g f[33] int f[2] Minimum storage used in the flow graph model is 8 bytes. However, due to alignment requirements the actual data storage is 12 bytes. 2 3 A Model for Software and Runtime System The concept of a runtime system applies to ....

D. E. Thomas, J. K. Adams, and H. Schmit, "A Model and Methodology for HardwareSoftware Codesign," IEEE Design & Test of Computers, pp. 6--15, Sept. 1993.

....design techniques, embedded systems are now being used in new application areas. To address the increasing complexity of embedded systems, recently there has been a surge of interest in use of predesigned reprogrammable components such as microcontrollers to reduce the design time and design cost [1, 2, 3, 4]. In such mixed implementations, portions of system functionality are realized by a program running on the processor. The use of software in system design o#ers a convenient and cost e#ective alternative to synthesis of hardware for large system designs. However, a purely software implementation ....

D. E. Thomas, J. K. Adams, and H. Schmit, "A Model and Methodology for Hardware-Software Codesign," IEEE Design & Test of Computers, pp. 6--15, Sept. 1993.

....coefficients. In [46] an inventive FPGA based cross correlator for radio astronomy is described. This system achieves high processing rates of 250MHz inside the FPGA by heavily pipelining each aspect of the data computation. To support speech processing, a bus based multi FPGA board, Tabula Rasa [95], was programmed to perform Markov searches of speech phenomes. This system is particularly interesting because it allowed the use of behavioral partitioning and contained a codesign environment for specification, synthesis, simulation, and evaluation design phases. Target Recognition Another ....

D. E. Thomas, J. K. Thomas, and H. Schmit. A Model and Methodology for Hardware-Software Codesign. IEEE Design and Test of Computers, pages 6--15, Sept. 1993.

....method 3.2. 1 Software hardware migration The acceleration of application software by migrating parts of the software into the hardware is an aspect of hardware software codesign [DM93] KAJW93] GCJDM94] Wol93] DM94b] DM94a] Software hardware migration entails the following problems [TAS93] ffl characterizing hardware and software performance ffl identifying hardware software partitions ffl transforming functional descriptions into such partitions ffl synthesizing the resulting hardware and software Thomas et al. TAS93] start system synthesis with a description of the ....

.... migration entails the following problems [TAS93] ffl characterizing hardware and software performance ffl identifying hardware software partitions ffl transforming functional descriptions into such partitions ffl synthesizing the resulting hardware and software Thomas et al. TAS93] start system synthesis with a description of the system s behavior in terms of interacting processes. Processes are further decomposed into tasks. These tasks are sequences of operations. Synthesis takes place at the task level. Therefore, synthesis problems are (i) to group operations into ....

Donald E. Thomas, Jay K. Adams, and Herman Schmit. A Model and Methodology for Hardware--Software Codesign. IEEE Design & Test of Computers, 10(3):6--15, September 1993.

....(hardware and software) and the communication units. Inter modules interaction is abstracted using communication primitives that hide the implementation details of the communication units. 1.2. Related Work Several researchers have described frameworks and methodologies for codesign [2] 5] 6] [7] [8] 9] Codesign environments differ by the way in which the Hw Sw are described, abstraction level and communication model used. Most of the previous work have been targeted towards either cosimulation or cosynthesis and very few of them tried to combine both. However, they do not address all ....

....for multiple platforms, but it uses a restricted class of architectures. Communication between hardware and software is one of the main issues when dealing with cosimulation and cosynthesis. Some approaches make use of a fixed communication scheme depending on a fixed architectural platform [1] [7] [13] 9] in which case the first two problems addressed earlier are easily handled. Although some of these architectures are flexible (e.g. supports a variable number of hardware and software processors) they use a fixed communication model to exchange information between protocols [10] 16] ....

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D.E.Thomas, J.K.Adams, H.Schmit, "A Model and Methodology for Hardware-Software Codesign," IEEE Design & Test of Computers, Vol.10, N3, pp.6-15, September 1993.

....and new high performance cost effective hardware technologies like fpgas and cplds, mixed hardware software solution has become very effective for several real time and embedded systems applications. There have been several approaches to solve the problem of hardware software partitioning [1, 5, 6, 7, 8, 9]. Fully automatic partitioners are in existence for quite some time now [5, 1, 6] Gupta and De Micheli [5] start with an all hardware solution and iteratively move one task at a time to software until no further improvement is possible. Ernst and Henkel [1] on the contrary follow a software ....

D.E. Thomas J.K. Adams, H. Schmit. "A Model and Methodology for Hardware-Software Codesign". In IEEE. Design & Test of Computers, pages 6--15, September 1992.

....main Codesign steps in this case are interlanguage communication synthesis and subsystem refinements [16] Most of existing tools in this area provides few refinements and they start the design at quite a low level e.g. RTL for Hardware and C language for Software. Coware [22] Seamless [9] and [24] are typical environments supporting such a codesign scheme. They start from a mixed description given in VHDL or VERILOG for hardware and C for software. All of them allow for cosimulation. However, only Coware allows for interface synthesis [2] Only few systems in the literature tried to tackle ....

D.E. Thomas and J.K. Adams and H. Schmit. 1993 (Sep.). A Model and Methodology for Hardware-Software Codesign. IEEEDTC, 10(3), pages 16-28.

....at different levels ranging from the implementation level where communication is performed through wires to the application level where communication is performed through high level primitives independent from the implementation. Figure 3. 2 shows three levels of inter module communication [14]. Module 2 Application Drivers I O Signals send, receive wait set reset signals read write I O registers Module 1 Application Drivers I O Signals Figure 3.2: Abstraction levels of inter module communication Title 4. MCI: A Multilanguage Co simulation Interface The figure 4.1 ....

D.E. Thomas, J.K. Adams and H. Schmit, "Model and methodology for hardware-software codesign", in IEEE Design and Test of Computers, 10(3):6-15, September 1993.

....et al. 1998] However, none of these systems has been used in synthesis to the best of our knowledge. With a somewhat different motivation, Communicating Sequential Processes have been applied to hardware software co design by Gupta et al. Gupta and de Micheli, 1993] and Thomas et al.[Thomas et al. 1993]. 7. CONCLUSION When applied in conjunction with reconfigurable technologies, TRAC can drastically lower the entry cost of taking on a hardware project by people who are not hardware designers by training. Compilers like TRAC have the potential to close the traditional distinction of hardware ....

Thomas, D. E., Adams, J. K., and Schmit, H. (1993). A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, pages 6--15.

....a hardware description language, e.g. VHDL or Verilog, as a starting point for codesign. Initially, everything can be assumed to be implemented in hardware. Afterwards, some parts of the functionality can be moved to software. There are numerous examples of this method available in the literature [10, 14, 21, 22]. In codesign, however, it might also be a good idea to start from a neutral graphical description, like MOOSE [18] However, it is also possible to start from a software oriented language, like C C , and later move some parts from software to hardware [8, 19] In our work we start from an ....

D. E. Thomas, J.K. Adams & H. Schmit. A Model and Methodology for Hardware-Software Codesign. IEEE Design & Test of Computers, Vol. 10, No. 3, 6-15.

....parts of the algorithm will end up in hardware ad which in software. In the context switching case the same component may be running in software at one point and in hardware at another. Co design techniques can be categorised into two broad areas. The first approach is the unified methodology [Themes, 1993], Ismail, et.al. 1994a] Ismail, et.al. 1994b] in which is a single language is used for top down design. The second approach is called heterogeneous [Kalavade A, 1994] where different design languages are used for each component. This peak detector application described here was implemented ....

Themes, D.E, and Adams, J.K. and Schmit, H. (1993) `A model and methodology for hardware-software CoDesign' IEEE Design & Test of Computers, Vol 10, Iss 3, pp6-15, Sept. 1993.

....methods, proposed for example by Gupta et al. in [GJM92] relies on a single custom simulator for hardware and software. This simulator uses a single event queue, and a high level, bus cycle model of the target CPU. A second class, described by Wilson et al. in [Wil94] by Thomas et al. in [TAS93] and by Rowson in [Row94] loosely links a hardware simulator with a software process. Synchronization is achieved by using the standard interprocess communication mechanisms offered by the host Operating System. One of the problems with this approach is that the relative clocks of software and ....

D.E. Thomas, J.K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, 10(3):6--15, September 1993.

.... There exist already many different approaches to system level synthesis that may be classified according to their class of input specifications: ffl Control dominant specification: Methods in this class consider control dominated specifications, e.g. communicating sequential processes [4] [24], C code [13] and extensions thereof [9] or finite state machine based specifications, e.g. 15] In the mapping phase, static) scheduling of tasks and communications cannot be done due to non determinism of execution times. Here, estimation mainly depends on profiling and simulation. ffl Data ....

D. E. Thomas, J. K. Adams, and H. Schmitt. A model and methodology for hardwaresoftware codesign. IEEE Design & Test of Computers, 10(3):6--15, September 1993.

....functionalities delegated to them. In this paper, we propose techniques for developing event handlers and device drivers for embedded systems. Frameworks for automated design of microcontroller based systems have been proposed in Presently at the University of Dortmund on Humboldt Fellowsh ip [1, 2, 3, 4]. The thrust of recent research in hardware software interfacing has been in the field of synthesizing interfaces for devices. An early work on the development of interfaces for available devices [5] described techniques for implementing the interface by hardware elements alone. A later work [6] ....

D. E. Thomas, J. K. Adams, and H. Schmit, "A model and methodology for hardware software codesign," IEEE Design and Test, pp. 6--15, Sept, 1993.

....A concurrent engineering of system design, known as codesign, is an emerging technology in design automation field for reducing design cost and shortening turnaround time. To avoid problems of traditional design process, codesign concept has gained more and more attention among system designers[3, 7, 8, 9]. For concurrent and interactive design, the codesign system needs to provide the following capabilities: unified hardware software representation, hardware software partitioning, heterogeneous simulation at different levels of abstraction, and hardware software synthesis. While there are ....

Donald E. Thomas, J. K. Adams, H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, pages 16--28, September 1993.

....H V a b c d V V H a b c d V V H a b c d H V V a b c d H V V Figure 6. Tree rotations 5. 0 Examples To demonstrate the effectiveness of our array mapping approach, we have synthesized two memory intensive applications: a speech phoneme recognizer based on Viterbi search [14] and a fuzzy controller [12] In both examples, the memory component library contains a small on chip memory (64 words by 8 bits) and three large memory components: 8K by 8, 32K by 8 and a 128K by 8. The number of the small memories is limited by the amount of on chip area that can be budgeted for ....

D. E. Thomas, J. Adams, and H. Schmit, "A Model and Methodology for Hardware-Software Codesign," IEEE Design and Test of Computers, Vol. 10, No. 3, pp. 6-15, Sept. 1993.

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Thomas 93 D. E.Thomas, J. Adams, and H. Schmit, "A Model and Methodology for HardwareSoftware Codesign," IEEE Design and Test of Computers, Vol. 10, No. 3, pp. 6-15, Sept. 1993.

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D. Thomas, J. Adams, and H. Schmitt, "A Model and Methodology for Hardware -Software Codesign," IEEE Design & Test of Computers, Vol. 10, No. 3, pp. 615, 1993.

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D. E. Thomas, J. K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, September 1993.

No context found.

D. Thomas, J. Adams, and H. Schmitt, "A model and methodology for hardware-software co-design," IEEE Design and Test, vol. 10, no. 3, pp. 6--15, Sept. 1993.

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D. E. Thomas, J. K. Adams, and H. Schmit, "A model and methodology for hardware-software code-sign," IEEE Des. Test Comput., pp. 6--15, Sept. 1993.

No context found.

D.E. Thomas, J.K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, 10(3):6-- 15, September 1993.

No context found.

D.E. Thomas, J.K. Adams, and H. Schmit. "A Model and Methodology for Hardware-Software Codesign," IEEE Design& Test of Computers, Vol. 10, no. 3, pp. 6-15, Sept. 1993.

No context found.

D. E. Thomas, J. K. Adams, and H. Schmit. A model and methodology for hardware-software codesign. IEEE Design and Test of Computers, pages 6--15, September 1993.

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