M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," 26th ACM/IEEE Design Automation Conference, pp. 7-12, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....response) filter, a 3 rd order IIR (infinite impulse response) filter, a 4 point DCT (discrete cosine transformation) circuit, and a 4 tap wavelet filter. We adopted the scheduling and module assignment from [1] for tseng and paulin. The other four data flow graphs were synthesized using HYPER [34]. The width of the data path logic is eight for all the circuits. A detailed description of the circuits is available in [35] In this paper, the area of a circuit is represented by the transistor count of registers and multiplexers in the circuit. Data path logic of a circuit is not considered ....

M. Potkonjak and J. Rabaey, "A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Folw Graphs," Proc. 36 th Design Automation Conf., pp. 7-12, June 1989.

....response) filter, a 3 rd order IIR (infinite impulse response) filter, a 4 point DCT (discrete cosine transformation) circuit, and a 6 tap wavelet filter. We adopted the scheduling and module assignment from [3] for tseng and paulin. The other four data flow graphs were synthesized using HYPER [24]. The width of the data path logic is eight for all of the circuits. In this paper, the area of a circuit is represented by the transistor count of registers and multiplexers in the circuit. Data path logic of a circuit is not considered in the transistor count. The number of transistors in test ....

M. Potkonjak and J. Rabaey, "A Scheduling and resource allocation algorithm for hierarchical signal flow graphs," Proc. 36 th Design Automation Conf., pp. 7-12, June 1989.

....impulse response filter, a third order infinite impulse response filter, a four point discrete cosine transformation circuit, and a six tap wavelet filter. We adopted the scheduling and module assignment from [4] for tseng and paulin. The other four data flow graphs were synthesized using HYPER [22]. The width of the datapath logic is eight for all the circuits. Details of the circuits are shown in Table I. Column headings of the table are described below: ckt name of the circuit; var number of variables in the DFG; const number of constants in the DFG; op number of operations in the ....

M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," in Proc. 36th Design Automation Conf., June 1989, pp. 7--12.

....The other four data flow graphs are a 6 th order FIR (finite impulse response) filter, a 3 rd order IIR (infinite impulse response) filter, a 4 point DCT (discrete cosine transformation) circuit, and a 6 tap wavelet filter. The other four data flow graphs were synthesized using HYPER [14]. The width of the data path logic is eight for all the circuits. The reference circuits, which were used to measure the area overhead of BIST designs, were obtained through an ILP for data path synthesis. The reference circuits are optimal in area. In this paper, the area of a circuit is ....

M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," Proc. 36 th Design Automation Conf., pp. 7-12, June 1989.

....Hierarchicalhigh levelsynthesiscanbedividedintotwosubproblems, i)derivinghierarchicalinformationfromaflattenedbehavioraldescription, and(ii)synthesizingacircuitusingahierarchicalbehavioraldescription. Thelatterproblem,whichisaddressedinthispaper, wasalsoconsideredin[1,2,3,4].In[1]and [3] theproblemofsynthesizingarea optimizedcircuitsfromhierarchicalbehaviorswasconsidered. Thetechniquepresentedin[4] whichwasgearedtowardsapplyingpower optimizingtransformations, supportstwolevelsofhierarchy.Pastresearchinflattened ....

....Hierarchicalhigh levelsynthesiscanbedividedintotwosubproblems, i)derivinghierarchicalinformationfromaflattenedbehavioraldescription, and(ii)synthesizingacircuitusingahierarchicalbehavioraldescription. Thelatterproblem,whichisaddressedinthispaper, wasalsoconsideredin[1,2,3,4] In[1]and [3] theproblemofsynthesizingarea optimizedcircuitsfromhierarchicalbehaviorswasconsidered. Thetechniquepresentedin[4] whichwasgearedtowardsapplyingpower optimizingtransformations, supportstwolevelsofhierarchy.Pastresearchinflattened high levelsynthesisforlowpowerhasconsideredallocationand ....

M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," in Proc. Design Automation Conf., pp. 7--12, June 1989.

....literature also presents several approaches to the problem of handling multidimensional executions with multidimensional productions and consumptions of data, however without strict periodicity and strict timing requirements. In the area of high throughput DSP, work is done on loop transformations [4, 11], in which descriptions with loops are modified in order to obtain, for instance, more parallelism and a higher throughput. In that approach the throughput is considered an objective rather than a constraint. In [13] loop transformations are handled by a method based on placement of polytopes. ....

M. Potkonjak and J. Rabaey. A scheduling and resource allocation algorithm for hierarchical signal flow graphs. Proc. of the DAC, 7--12, 1994.

....parts of the same design. A hierarchical synthesis system can evolve with time, using the experience gained from previous designs, to synthesize better quality circuits faster. The problem of synthesizing area optimized circuits from hierarchically specified behavioral descriptions was tackled in [12] and [13] In [11] it was demonstrated that partitioning of flat behavioral descriptions to maximize regularity led to efficient and economical designs. Tradeoffs in controller synthesis for hierarchically designed systems were examined in [14] The problem of partitioning, i.e. deriving a ....

M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," in Proc. Design Automation Conf., pp. 7--12, June 1989.

....In order to be more realistic the communication delay has to be considered in high level synthesis. Since allocation involves assigning the operations to hardware, it also determines the communication overhead. Thus, in high level synthesis the scheduling and allocation are closely interrelated [5,12,19,26,28,31 33,37,47,49,50]. In order to have an optimal design, both should be performed simultaneously. Due to the time complexity, however, many systems perform them separately, or introduce iteration loops between the two tasks, as it was the case in our GAM scheduling allocation approach. We may conclude that the key ....

Potkonjak M. and Rabaey J. (1989) A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs. Proc 26th ACM/IEEE Design Automation Conf., p. 7-12.

....or to modify existing tools. An overview of the envisioned system is shown in Fig. 7.1. An automated compilation path from a high level data flow language silage [91] to the paddi chip, which includes partitioning, scheduling, and code generation is forseen. caddi will be similar to the approach [95] taken in hyper and will contain all steps required for compilation namely allocation, assignment, and scheduling modules, followed by translation into assembly language and ultimately into a configuration file. In hyper the synthesis procedure is implemented as a search process. From an initial ....

....or applying graph transformations. hyper uses a single global quality measure, called resource allocation, to drive the search process. The allocation and assignment approach differs from the approach presented above in that a modification of the rejectionless antivoter assignment algorithm of [95] is envisioned. The rapid prototyping framework will allow the designer to experiment and analyze the speed vs. cost trade off for various implementations as well as the effects of quantization and transformations on system performance. Initial results and the on going investigation CHAPTER 7. ....

M. Potkonjak and J. Rabaey. "A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs". In Proceedings 26th ACM/IEEE Design Automation Conference, pages 7--12, June 1989.

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M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," 26th ACM/IEEE Design Automation Conference, pp. 7-12, 1989.

....point to note is that no additional shifters are needed. In the event of a shifter failure, the scheduling flexibility brought by the redundant multiplier is exploited. B. Allocation, Assignment, and Scheduling Algorithm The global strategy of the Hyper behavioral level synthesis system [19] is well suited for use as the starting point for developing new algorithms targeting HBISR. In this system, allocation first proposes a hardware solution, then assignment and scheduling are performed to check its feasibility. To take into account BISR requirements, it was necessary to develop a ....

....allocation. It is calculated during the assignment and scheduling. The scheduling difficulty, SD( is calculated for each operation, and is inversely proportional to the slack time between the As Late As Possible (ALAP) scheduling time and a relaxed As Soon As Possible (ASAP) scheduling time [19]. This value is summed over all nodes of type , to give the unnormalized stress stress Nodes SD (3) Since we are interested in the minimum area solution, we normalize the stress value by the hardware cost of the unit, giving the scheduling stress for hardware type as a function of the ....

M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," in Proc. ACM/IEEE Design Automation Conf., 1989, pp. 7--12.

....point to note is that no additional shifters are needed. In the event of a shifter failure, the scheduling flexibility brought by the redundant multiplier is exploited. 4. 2 Allocation, Assignment, and Scheduling Algorithm The global strategy of the Hyper behavioral level synthesis system [Pot89] is well suited for use as the starting point for developing new algorithms targeting HBISR. In this system, allocation first proposes a hardware solution, then assignment and scheduling are performed to check its feasibility. To take into account BISR requirements, it was necessary to develop a ....

....allocation. It is calculated during the assignment and scheduling. The scheduling difficulty, SD(k) is calculated for each operation, k, and is inversely proportional to the slack time between the As Late As Possible (ALAP) scheduling time and a relaxed As Soon As Possible (ASAP) scheduling time [Pot89]. This value is summed over all nodes of type j, to give the un normalized stress: EQ 3) Since we are interested in the minimum area solution, we normalize the stress value by the hardware cost of the unit, giving the scheduling stress for hardware type j as a function of the scheduling ....

M. Potkonjak and J. Rabaey, "A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs," ACM/IEEE Design Automation Conference, pp. 7-12, 1989.

....application of the algorithm on 4 examples. The average power reduction was by factor of 3.11 times. 4.1. 4 Hierarchical Allocation and Scheduling With a steady increase in the size of ASIC designs, the need for hierarchical scheduling in high level synthesis is becoming more and more apparent [Pot89]. Also, as the exploration of the connection between retargetable compilation [Mar93] and high level synthesis has been gaining research momentum, the relevance of hierarchical treatment of scheduling is additionally emphasized. This is so, because a typical application of retargetable compilers ....

M. Potkonjak, J.Rabaey "A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs", 26th ACM/IEEE Design Automation Conference, Las Vegas, NV, pp. 7-12, June 1989.

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M. Potkonjak and J. Rabaey, "A scheduling and resource allocation algorithm for hierarchical signal flow graphs," in Proc. Design Automation Conf., June 1989, pp. 7--12.

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M. Potkonjak and J. Rabaey. A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs. In Proceedings of the 26  Design Automation Conference, pages 7--12, June 1989.

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M. Potkonjak and J. Rabaey, "A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs," Proc. 26 Design Automation Conf., pp. 7-12, June 1989.

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M. Potkonjak anti J. Rabaey; "A Scheduling and Resource Allocation Algorithm fm Hierarchical Signal Flow Graphs," Pros. Design Automation Cord IEEE Computer Society Press, Los A/amilos, Calif, 1989, pp. 7-12.

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