J. Briner. Fast parallel simulation of digital systems. In Proc. of Multiconf. on Advances in Parallel and Distributed Simulation, pages 71--77, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....in those schemes. However, their performance is only slightly better than the TW due to the overhead of frequent global synchronizations. A major problem of parallel logic simulation techniques is that they do not produce consistent performance on different circuits and different input vectors [16, 18, 21]. Recently, clock cycle based simulation has attracted a lot of interest even though it is only usable for synchronous circuits. However, the performance of parallel clock cycle based simulation is very limited due to blocking interprocessor communication or replication allocation. To reduce the ....

J. V. Briner Jr., "Fast Parallel Simulation of Digital Systems," Proc. of the

....perhaps more importantly, greater transparency of the synchronization mechanism to the simulation programmer. Time Warp has demonstrated a fair amount of success in speeding up simulations of combat models [32] communication networks [3] 27] queuing networks [8] and digital logic circuits [2], among many others. One major critique of Time Warp is its apparent large and inefficient use of memory. Time Warp uses a checkpointing technique to implement the rollback mechanism. Past states of the processes need to be saved to enable rollback. In addition, the Time Warp system may hold a ....

J. Briner, Jr., "Fast Parallel Simulation of Digital Systems," Proc. Multiconf. Advances in Parallel and Distributed Simulation, vol. 23, no. 1, pp. 71-77, Jan. 1991.

....a speedup of 16 to 29 on an 64 processor parallel machine, 6 to 9 on a 14 processor Encore Multimax and 2 to 4 on a 16 processor DASH respectively. DeBenectitus et al. DeBe91] examines gate level simulation, using a conservative algorithm which eliminates cycles in the logic diagram. Briner [Brin91] and Sporrer and Bauer [Spor93] use Time Warp for switch and gate level simulations on a 32 processor BBN GP100 machine reporting speedups from 5 to 12 and 4 to 8 respectively. Comparison studies of various synchronization protocols for gate level simulation have been performed by Lin et al. ....

Briner, J. Jr., "Fast Parallel Simulation of Digital Systems", SCS Advances in Parallel and Distributed Simulation, 23, January 1991, pp. 71-77.

....event simulation, where LPs model distinct parts of the simulated system, and tasks correspond to simulation events. In this context optimistic synchronization has allowed good speedup for simulations of combat models [27] queuing networks [9] communication networks [5, 17] logic circuits [3] and others. One of the core problems of the optimistic synchronization protocol is how to support fast state recovery with low checkpointing overhead. To tackle this problem a number of checkpointingrecovery schemes have been proposed, which exhibit different tradeoffs between the checkpointing ....

J. Briner, Jr., "Fast Parallel Simulation of Digital Systems", Proc. Multiconf. Advances in Parallel and Distributed Simulation, Vol.23, No.1, pp.71-77, January 1991.

....driving it modeled only at a very functional level. Similar ranges of event size (granularity) occur in both telecommunications and transportation simulations. A third lesson is that the amount of parallelism that is available in these problems also varies greatly. For example it has been shown [Briner, 1990, 1991] that even small gate level models of circuits have the potential to speed up by factors of thousands. In contrast, various scenarios for the SS7 models have potential parallelism from 5 to 100. Message Passing Overheads Any parallelizing simulator that is to be successful must be able to handle ....

Briner, J.(1991) "Fast Parallel Simulation of Digital Systems," Advances in Parallel and Distributed Simulation, Anaheim, CA, pp. 7177, January.

....been developed and used a benchmarks for various CAD tools (especially for studies of synthesis algorithms) The only restriction here is that the circuits should be large and have enough parallelism to justify parallel simulation. Parallel simulation of logic circuits has been studied extensively [4, 8, 15] even though no particular protocol has been proved to be more useful that the other. This also makes it an candidate for use as a benchmark. Another reason why logic simulation can used used as a benchmark is because of the growing sizes of VLSI circuits that make it a good candidate for parallel ....

Briner Jr., J. Fast Parallel Simulation of Digital Systems. In Proceedings of the SCS Multiconference on Advances in Parallel and Distributed Simulation (1991), pp. 71--77.

....Numerous analytic and empirical studies of the performance of Time Warp have been performed, e.g. see [8, 7] for recent surveys. Time Warp has demonstrated good success in speeding up simulations of combat models [17] communication networks [14] queueing networks [5] and digital logic circuits [1], among others. The bulk of the research that has beenperformed thus far has focused on execution of multiprocessor and multicomputer systems with fast interprocessor communications. A question of considerable pragmatic interest is whether Time Warp can provide good performance in distributed ....

J. Briner, Jr. Fast parallel simulation of digital systems. In Advances in Parallel and Distributed Simulation, volume 23, pages 71--77. SCS Simulation Series, January 1991.

.... of events as they occur, and recovers using a rollback mechanism [10] Time Warp has demonstrated some success in speeding up a variety of simulation applications, including combat models [17] communication networks [14] wireless networks [4] queuing networks [6] and digital logic circuits [1], among others. We assume that the reader is familiar with the Time Warp mechanism described in [10] With few exceptions, most research on distributed simulation to date assumes the simulation program is allocated a fixed number of processors when execution begins, and has exclusive access to ....

J. Briner, Jr. Fast parallel simulation of digital systems. In Advances in Parallel and Distributed Simulation, volume 23, pages 71--77. SCS Simulation Series, January 1991.

....and, perhaps more importantly, greater transparency of the synchronization mechanism to the simulation programmer. Time Warp has demonstrated a fair amount of success in speeding up simulations of combat models [31] communication networks [3, 26] queueing networks [8] and digital logic circuits [2], among many others. One major critique of Time Warp is its apparent large and inefficient use of memory. Time Warp uses a checkpointing technique to implement the rollback mechanism. Past states of the processes need to be saved to enable rollback. In addition, the Time Warp system may hold a ....

J. Briner, Jr. Fast parallel simulation of digital systems. Proceedings of the Multiconference on Advances in Parallel and Distributed Simulation, 23(1):71--77, January 1991.

.... protocol that detects out of order executions of events as they occur, and recovers using a rollback mechanism [8] Time Warp has demonstrated some success in speeding up simulations of combat models [14] communication networks [12] queuing networks [4] and digital logic circuits [1], among others. We assume that the reader is familiar with the Time Warp mechanism described in [8] Here, we are concerned with the efficient implementation of Time Warp on shared memory multiprocessor computers. While prior work in this area has focused on data structures [4] synchronization ....

J. Briner, Jr. Fast parallel simulation of digital systems. In Advances in Parallel and Distributed Simulation, volume 23, pages 71--77. SCS Simulation Series, January 1991.

....rarely encountered in the application. One such example is the simulation of digital logic networks. VLSI simulation is notorious for its computational demands, the significance of successful parallelization would be large. Standard CMB and Time Warp approaches have been attempted [85] [64], with only mixed results. Recognizing that feedback loops pose one of the hardest problems for a conservative synchronization algorithm, 20] propose an approach where the network to be simulated is transformed into another (larger) one containing no feedback loops. This algorithm is tested on a ....

J. Briner, Jr. Fast parallel simulation of digital systems. In Advances in Parallel and Distributed Simulation, volume 23, pages 71--77. SCS Simulation Series, Jan. 1991.

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J. Briner. Fast parallel simulation of digital systems. In Proc. of Multiconf. on Advances in Parallel and Distributed Simulation, pages 71--77, 1991.

No context found.

J. Briner, "Fast Parallel Simulation of Digital Systems", Proc. Multiconf. Advances in Parallel and Distributed Simulation, vol.23, n.1, pp.71-77, 1991.

No context found.

J. Briner, "Fast Parallel Simulation for Digital Systems", Proc. of Multiconf. Advances in Parallel and Distributed Simulation, vol.23, n.1, pp.71-77, January 1991.

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