G. Gopalakrishnan and R. Fujimoto. Design and verification of the rollback chip using hop: A case study of formal methods applied to hardware design. ACM Transactions on Computer Systems, 11(2):109-- 145, 1993. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Specification and Validation of Control Intensive ICs in hopCP - Akella, Gopalakrishnan (1994) (1 citation) Self-citation (Gopalakrishnan) (Correct)
....the description of the 8251 in a semantically well specified notation, we believe that some of the difficulties of formally verifying such systems will be brought to the surface. Currently there is a growing trend towards applying formal methods in the design of real world hardware systems [39, 16, 15]. Most of the current efforts do not address ICs that, in addition to exhibiting control intensive behavior also support non trivial computations. Our contributions in this paper include the following: i) the design of a semantically well specified and simple HDL tailored for the specification of ....
Gopalakrishnan, G., and Fujimoto, R. Design and verification of the rollback chip using hop: A case study of formal methods applied to hardware design. Tech. Rep. UU-CS-TR-91-015, University of Utah, Department of Computer Science, 1991.
SHILPA: A High-Level Synthesis System for Self-timed Circuits - Akella, Gopalakrishnan (1992) (19 citations) Self-citation (Gopalakrishnan) (Correct)
....interconnection of hopCP modules. In general, behavioral descriptions that are inferred from structural descriptions are useful for formal verification, high level test generation, and behavioral simulation, as we have shown in our earlier work with a synchronous HDL that is similar to hopCP [22, 2, 30]. We hope to derive these advantages in the hopCP design environment also. conCur is a flow analysis tool to detect if two actions occurring in different sequential processes are serial (due to synchronizations between the processes) or are potentially concurrent (seriality is not decidable in ....
Gopalakrishnan, G., and Fujimoto, R. Design and verification of the rollback chip using hop: A case study of formal methods applied to hardware design. Tech. Rep. UU-CS-TR-91-015, University of Utah, Department of Computer Science, 1991.
Parallel Simulation Today - Nicol, Fujimoto (1994) (39 citations) Self-citation (Fujimoto) (Correct)
....be reduced to only a few percent of the computation. Special caches are used to improve performance. A simplified prototype implementation of the rollback chip has been developed in the commercial sector [11] Also, the hardware design of the rollback chip has been verified using formal techniques [39]. 5.3 Global Synchronization Networks One of the reasons protocols for parallel simulation are nontrivial is the fact that critical synchronization information is distributed across the multiprocessor system. For instance, in conservative protocols, informa18 tion indicating which events can be ....
G. Gopalakrishnan and R. M. Fujimoto. Design and verification of the rollback chip using HOP: A case study of formal methods applied to hardware design. Technical Report UUCS-91-015, Dept of Computer Science, Univ. of Utah, September 1991.
A Formal View of Multicomputers - Gallud, García, Quiles (Correct)
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G. Gopalakrishnan and R. Fujimoto. Design and verification of the rollback chip using hop: A case study of formal methods applied to hardware design. ACM Transactions on Computer Systems, 11(2):109-- 145, 1993.
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