S. A. Kravitz, R. E. Bryant, and R. A. Rutenbar. Logic simulation on massively parallel architectures. Proc. 16th Ann. Int. Symp. on Computer Architecture, pages 336--343, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and instruction based interpretation. 6.2.1 Early Experiments Early experiments used interpretive approaches to optimize the performance of specific applications on SIMD machines. Some studies studies used concurrent interpretation for logic circuit simulation [ Chung and Chung, 1989, Kravitz et al. 1989 ] Traditionally, logic circuit simulation was considered not suitable for massively parallel implementation because: 1) the small degree of parallelism present in discrete event based implementations, and (2) it is a fine grained application; requiring little computation and significant ....

....significant communication. Consider, the evaluation of the output of a gate (typically one instruction) is followed by several communication steps to forward the output of the gate to its fan out nodes. Kravitz studied the use of concurrent interpretation for simulating sequential logic circuits [ Kravitz et al. 1989 ] The circuit is pre processed into a behaviorally equivalent representation using AND and OR operations. The circuit is mapped to a rank processor rectangle, where each rank represents a simulation step, on the SIMD machine in the following way: a gate can be placed in any rank after the one ....

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S. A. Kravitz, R. E. Bryant, and R. A. Rutenbar. Logic simulation on massively parallel architectures. Proc. 16th Ann. Int. Symp. on Computer Architecture, pages 336--343, 1989.

....Communication is provided through either a global router or a cheaper, but more restrictive X net. A PE either participates in an instruction or is masked out of the instruction. 2. 2 Related or The work outlined in this paper was influenced by two studies on parallel logic simulation, 2] and [9]. Essentially these approaches translate a logic description into and and or instructions. Each resulting operation ( and or or ) is assigned to a distinct processing element with the control algorithm broadcasting both execute operations and the PEs masking themselves into and out of the ....

Kravitz, S. A., Bryant, R. E., and Rutenbar, R. A. Logic simulation on massively parallel architectures. Proc. 16th Ann. Int. Symp. on Computer Architecture (1989), 336--343.

....problems. An iteration advance method was employed to rearrange the iterations for SIMD execution, which was called SIMLAD (SIMD model with local indirect addressing) in [36] and loop flattening in [37] Recent studies have been conducted on the simulation of logic circuits on a SIMD machine [6, 20]. The major difference between these works and our approach is that we handle general asynchronous and loosely synchronous problems instead of studying individual problems. The instruction level approach has been studied by a number of researchers [8, 9, 22, 25, 41, 40] As mentioned above, the ....

S. A. Kravitz, R. E. Bryant, and R. A. Rutenbar. Logic simulation on massively parallel architectures. In Proc. 16th Ann. Int. Symp. on Computer Architecture, pages 336--343, 1989.

.... execution of functional programs [9, 11, 14] Additional work has been conducted in the interpretation of logic programming languages such as Prolog and FLAT GHC [12, 19] More recently, several studies have considered the simulation of logic circuits by interpretation on a SIMD processor [2, 13]. An alternative, but related, approach to exploiting MIMD interpretation is presented by Collins [3] He proposes to replace the conditional regions of a SIMD program with interpretable MIMD instructions. The application is programmed as a data parallel algorithm, but regions of the code where ....

Kravitz, S. A., Bryant, R. E., and Rutenbar, R. A. Logic simulation on massively parallel architectures. Proc. 16th Ann. Int. Symp. on Computer Architecture (1989), 336-343.

....applications led to its virtual exclusion as a programmingmodel for MIMD machines. More recently, however, researchers have demonstrated that dataparallel languages are useful for applications as diverse as parsing [22] DNA sequence comparison [7, 14] object recognition [26] VLSI design [8, 6, 13] and computer graphics [5] and most of the parallel algorithms found in the literature for grids, hypercubes and Parallel RAM models are either data parallel or easily converted into such a form. Furthermore, the semantic simplicity of data parallel languages, and their ability to easily express ....

....segdes Figure 2: A partial list of VCODE instructions. All the vector instructions take values off the top of the stack and return their result to the top of the stack. 5 1 3 4 3 9 2 6] 2 5 3 8 1 3 6 2] 7 6 6 12 4 12 8 8] l i f e p o t] 2 1 0 3 2 1 0] 4 3] permute [f i l e t o p] [1 3 5 7 11 13 15] [4 3] scan [0 1 4 9 0 11 24] Figure 3: Some vector instructions. Vectors are shown between square brackets. The instruction takes the top two vectors off the stack, adds them elementwise and returns the result to the top of the stack. The two source vectors must be of the same length. The ....

S. A. Kravitz, R. E. Bryant, and R. A. Rutenbar. Logic Simulation on Massively Parallel Architectures. In Proceedings 16th Annual International Symposium on Computer Architecture, pages 336--343, Jerusalem, Israel, 1989.

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S. A. Kravitz, R. E. Bryant, and R. A. Rutenbar. "Logic Simulation on Massively Parallel Architectures ". In: Proceedings of the 16th Annual International Symposium on Computer Architecture, pp. 336--343, ACM, 1989.

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