K. Gharachorloo. Personal communication, April 1998.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....regardless of the frequency with which these errors may occur. Nevertheless, the issues might seem less important if 2. At least one Alpha implementation leverages the relaxation of data dependence order and thus could produce undesired results if the memory barrier between r1 and r2 is omitted [16]. Figure 4. Correct Code for Weak Ordering without Data Dependence Code for T writer w1: store mem[B.data] 80 w2: load reg0 mem[Head] w3: store mem[B.next] reg0 w3b:memory barrier Code for T reader r1b:memory barrier r1: load reg1 mem[Head] w4: store mem[Head] B r2: load reg2 ....

K. Gharachorloo. Personal Communication, July 2001.

.... actually implementing the protocol [6] 17] To our 1 knowledge, the shortest SW DSM read latency to date is that of Shasta [34] The 15 microsecond round trip read latency is roughly divided into 5 microseconds, of real communication and 10 microseconds of interrupt and agent overhead [12]. Most other SW DSM implementations have substantially larger interrupt overheads, and latencies closer to 100 microseconds have been reported [37] In this paper we suggest a new efficient approach for software based coherence protocols. While other work has proposed elaborate schemes for ....

K. Gharachorloo. Personal communication, October 2000.

.... actually implementing the protocol [BS97] IS99] To our knowledge, the shortest SW DSM read latency to date is that of Shasta [SGA97] The 15 microsecond round trip read latency is roughly divided into 5 microseconds, of real communication and 10 microseconds of interrupt and agent overhead [Gha00] Most other SW DSM implementations have substantially larger interrupt overheads, and latencies closer to 100 microseconds have been reported [SFH # 96] In this paper we suggest a new efficient approach for software based coherence protocols. While other work have proposed elaborate schemes ....

....the expected latency of a remote network. We also wanted to compare our SW DSM implementation to one with a more common, still short, remote latency caused by the extra protocol overhead. We have used the shortest latency reported to date as our benchmark number: 15 microseconds (Shasta [SGA97] Gha00] This is modeled as extra network delay. The extra CPUs occupancy by the protocol agent in the remote end have not been taken into account, nor have we modeled any contention effects from single threaded agent in that scheme. 12 4 Performance Study In this section we describe experimental ....

K. Gharachorloo. Personal communication, October 2000.

....Processor Consistency The definitions of processor consistency given above correctly capture the definitions originally given by Goodman [15] and by Gharachorloo et al. 12] However, they may allow certain anomalous executions. For example, consider the history given in Figure 10. Gharachorloo [9] alerted us to the existence of such anomalous histories. This history is allowed by both definitions because the following legal serializations exist: S x = w q (x)1; r p (x)1; S y = w p (y)1; r q (y)1; S p = w q (x)1; r p (x)1; w p (y)1; S q = w p (y)1; r q (y)1; w q (z)1: The Power of ....

Kourosh Gharachorloo, October 1992. Personal communication.

....many RISC processors have been optimized to give the CPU priority to the L2 cache. In addition, they are typically optimized for providing high bandwidth to the L2 cache for the CPU and incoming requests. These optimizations often have the side effect of increasing the latency for dirty misses [7]. Unfortunately, the Pentium Pro counters provide no events for determining the latency of dirty misses. It is still useful, however, to quantify the frequency of this operation, and determine how it is affected by L2 cache size. Table 8 presents the percentage of L2 cache misses to dirty data in ....

K. Gharachorloo. Personal communication, April 1998.

....cache and a write back second level cache. There is a write buffer between the two caches and if a relaxed consistency model is being implemented, loads can bypass the stores that are in the write buffer. The first level cache has a one word line size and a fetch size on read misses of four words [48]. Cache coherence is enforced by a hardware full directory scheme with the directories being associated with the home memories. The memory latency depends upon the type of memory reference (read, write, synchronization) the memory location of the missing line (home or remote) and the state of ....

Kourosh Gharachorloo. personal communication.

....cache and a write back second level cache. There is a write buffer between the two caches and if a relaxed consistency model is being implemented, loads can bypass the stores that are in the write buffer. The first level cache has a one word line size and a fetch size on read misses of four words [12]. Cache coherence is enforced by a hardware full directory scheme with the directories being associated with the home memories. The memory latency depends upon the type of memory reference (read, write, synchronization) the memory location of the missing line (home or remote) and the state of ....

Kourosh Gharachorloo. personal communication.

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K. Gharachorloo. Personal communication, April 1998.

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