S. A. Mahlke, W. Y. Chen, P. P. Chang, and W. Hwu. Scalar Program Performance on MultipleInstruction Issue Processors with a Limited Number of Registers. In Hawaii International Conference on System Sciences, pages 34--44, 1992.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....by a significant amount. For scalar programs, the evidence for this statement is strong. Mahlke, et al. studied a number of scalar programs written in C and compiled on a full featured optimizing compiler. They found that little performance benefit was realized after approximately 16 registers. [18] They state that there may be other optimization which will increase register usage, but they do not elaborate. We found little work which showed that more registers were ineffective for numerical applications, however. One exception was that of Kiyohara, et al. 17] In this work, the authors ....

S. Mahlke, et al, "Scalar Program Performance on Multiple-Instruction-Issue Processors with a Limited Number of Registers," Proceedings of the 25th Annual Hawaii International Conference on System Sciences, 1992.

....optimizing compilers. This section outlines some previous work in expanding the register set of an architecture so that the compiler can do more effective allocation and spilling. Mahlke et al. examined the trade off between architected register file size and multiple instruction issue per cycle [Mahl92a]. They found that aggressive optimizations such as loop unrolling, and induction variable expansion are effective for machines with large, moderate, and even small register files, but that for small register files, the benefits are limited because of the excessive spill code introduced. Additional ....

....integer codes, the kind we are focusing on in this work, previous research to determine the best number of registers has not arrived at a clear consensus. For example, one study suggests that the number of processor registers that can be effectively used is limited to a couple dozen [Mahl92a]. Others have suggested that existing compiler technology cannot make effective use of a large number of registers [Beni93] Studies on the RISC I architecture refer to earlier work which shows that 4 to 8 windows of 22 registers each (for a total of 80 to 144 registers) is sufficient to house the ....

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Scott A. Mahlke, William Y. Chen, Pohua P. Chang and Wen-mei W. Hwu. Scalar Program Performance on Multiple-Instruction-Issue Processors with a Limited Number of Registers. Proc. 25th Hawaii Intl. Conf. System Sciences, pp. 34-44, Jan 6-9, 1992. 221

....jian mips.complang.tuwien.ac.at; Tel: 43 1 588014474; Fax: 43 1 5057838. z Dr. Eisenbeis is with INRIA Rocquencourt, Domaine de Voluceau, BP 105 78153, Le Chesnay Cedex, France. 1 The interaction between register allocation and loop free code scheduling has been studied since the mid 1980s [10, 18, 13, 16, 19], and register allocation for software pipelined loop has been studied by many researchers and some efficient techniques have been proposed [20, 12, 17, 15] However, the interaction between register allocation and software pipelining was lately considered in few studies. Mangione Smith, et al. ....

S.A. Mahlke, W.Y. Chen, P.P. Chang, and W.W. Hwu. Scalar program performance on multiple-instruction-issue processors with a limited number of registers. In proceedings of the 25th HAWAII International Conference on System Sciences, January 1992.

....integer codes, the kind we are focusing on in this work, previous research to determine the best number of registers has not arrived at a clear consensus. For example, one study suggests that the number of processor registers that can be effectively used is limited to a couple dozen [1]. Others have suggested that existing compiler technology cannot make effective use of a large number of registers [2] Studies on the RISC I architecture refer to earlier work which shows that 4 to 8 windows of 22 registers each (for a total of 80 to 144 registers) is July 17, 2000 7:25 pm 2 ....

....path length by elimination of load and store instructions, and it avoids using the limited bandwidth cache in favor of the more highly ported register file. 5. Related Work Mahlke et al. examined the trade off between architected register file size and multiple instruction issue per cycle [1]. They found that aggressive optimizations are effective for machines with large, moderate, and even small register files, but that for small register files, the benefits are limited because of the excessive spill code introduced. Additional instruction issue slots can ameliorate this by ....

Scott A. Mahlke, William Y. Chen, Pohua P. Chang and Wen-mei W. Hwu. Scalar Program Performance on Multiple-Instruction-Issue Processors with a Limited Number of Registers. Proc. 25th Hawaii Intl. Conf. System Sciences, pp. 34-44, Jan 6-9, 1992.

....this work, previous research to determine the best number of registers has not arrived at a clear consensus. In many cases this is due to different initial assumptions. For example, one study suggests that the number of processor registers that can be effectively used is limited to a couple dozen [1]. Others have suggested that existing compiler technology cannot make effective use of a large number of registers [2] Studies on the RISC I architecture refer to earlier work which shows that 4 to 8 windows of 22 registers each (for a total of 80 to 144 registers) is sufficient to house the ....

....following subsections. 5. 1 Register Requirements Sites presented perhaps the first in depth discussion of the advantages of being able to support large numbers of registers [9] Mahlke et al. examined the trade off between architected register file size and multiple instruction issue per cycle [1]. They found that aggressive optimizations such as loop unrolling and induction variable expansion are effective for machines with large, moderate, and even small register files, but that for small register files, the benefits are limited because of the excessive spill code introduced. Additional ....

Scott A. Mahlke, William Y. Chen, Pohua P. Chang and Wen-mei W. Hwu. Scalar Program Performance on Multiple-Instruction-Issue Processors with a Limited Number of Registers. Proc. 25th Hawaii Intl. Conf. System Sciences, pp. 34-44, Jan 6-9, 1992.

....Reference [17] is the M.S. thesis William Chen wrote a code generator for the MIPS architecture for use with the IMPACT compiler. Reference [18] is a technical report on the topic of code expanding optimizations and the added requirements to be met by instruction cache logic. Reference [19] examines the performance problems of machines that use multiple instruction issue architectures, but have a limited number of registers. Reference [20] uses the IMPACT compiler to compare results of static and dynamic code scheduling on processors using multiple instruction issue architectures. ....

S. A. Mahlke, W. Y. Chen, P. P. Chang, and W. W. Hwu, "Scalar program performance on multiple-instruction-issue processors with a limited number of registers," in Proceedings of the 25th Annual Hawaii International Conference on System Sciences, January 1992.

....spillings and severely degrade the performance of the pipelined loop [3] However, simultaneous register allocation and software pipelining is still less understood and remains open. The interaction between register allocation and loop free code scheduling has been studied since the mid 1980s [10, 18, 13, 19, 20, 21], and register allocation for software pipelined loop has been studied by many researchers and some efficient techniques have been proposed [22, 12, 17, 15] However, the interaction between register allocation and software pipelining was lately considered in few studies. Mangione Smith, et al. ....

S.A. Mahlke, W.Y. Chen, P.P. Chang, and W.W. Hwu. Scalar program performance on multiple-instruction-issue processors with a limited number of registers. In proceedings of the 25th HAWAII International Conference on System Sciences, January 1992.

.... It has been well known that register allocation may introduce anti dependences due to the re use of registers, which limit the loops ILP to be exploited by software pipelining [11, 3] The interaction between register allocation and loop free code scheduling has been studied since the mid 1980s [12, 13, 8, 14, 15]. The register allocation for software pipelined loop and lifetime sensitive software pipelining approaches have been studied by some researchers and some efficient techniques have been proposed [16, 17, 11, 10, 18, 19] However, the interaction between register requirement and loops maximum ILP ....

S.A. Mahlke, W.Y. Chen, P.P. Chang, and W.W. Hwu. Scalar program performance on multiple-instruction-issue processors with a limited number of registers. In proceedings of the 25th HAWAII International Conference on System Sciences, January 1992.

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S. A. Mahlke, W. Y. Chen, P. P. Chang, and W. Hwu. Scalar Program Performance on MultipleInstruction Issue Processors with a Limited Number of Registers. In Hawaii International Conference on System Sciences, pages 34--44, 1992.

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S. Mahlke, W. Chen, P. Chang, and W. Hwu, "Scalar Program Performance on Multiple-Instruction-Issue Processors with a Limited Number of Registers", Proceedings of the 25th Annual Hawaii International Conference on System Sciences, 1992.

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