R.E. Hank. Machine independent register allocation for the IMPACT-I C compiler. PhD thesis, Department of Electrical and Computer Engineering, Unviersity of Illinois at Urbana-Champaign, May 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....a large amount of time to implement Briggs style register allocation in our framework, and it is difficult to achieve the best possible performance without extensive testing and tuning. Another register allocation based on the priority based coloring approach is the IMPACT register allocation [21]. Since, the IMPACT I compiler [10] has in termediate language which is compatible to Trimaran, we could fairly easily test the performance of IMPACT register allocation by converting our intermediate language. IMPACT register allocation made many improvements to Chow s ap proach like Briggs ....

R.E. Hank. Machine independent register allocation for the IMPACT-I C compiler. PhD thesis, Department of Electrical and Computer Engineering, Unviersity of Illinois at Urbana-Champaign, May 1995.

....has facilitated the creation of several code generators for several different architectures [7] The most actively supported architectures are the Sun SPARC, the HP PA RISC, and the Intel X86. The two main components of code generation are the instruction scheduler and the register allocator [15]. Several scheduling models exist, including acyclic global scheduling [16] 17] sentinel scheduling [18] and software pipelining using modulo scheduling [19] The IMPACT and HPL Playdoh [20] architectures, two experimental instruction level parallelism (ILP) architectures, are also supported. ....

....parameter space and the swap space respectively. The out going parameter space represents one of the common ways of communicating parameter passing in intermediate representations. The swap space requirement appears only if the Lcode function has gone through the IMPACT register allocator [15]. This space is used for register spilling when there are not enough physical architectural registers. 5.2 Conversion of Lcode to C This phase uses all the information in the Lcode data structures and the emulator s data structures to transform Lcode instructions into C statements. Since all of ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler, " M.S. thesis, University of Illinois, Urbana, IL, 1993.

....These loops are then scheduled using the modulo scheduler. The remaining code is scheduled with the acyclic global scheduler. Both techniques can take advantage of control and data speculation if the target architecture allows. Register allocation is performed using the graph coloring method [44]. Profile information, if available, is used to assist the register allocator in making intelligent decisions. After register allocation a set of machine specific peephole optimizations is performed. These optimizations are designed to remove inefficiencies introduced during the Lcode to Mcode ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler," M.S. thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1995.

....scheduling and the remaining code is scheduled using the global acyclic scheduler. Additionally, code transformations to support the memory conflict buffer technique described in Chapter 4 are applied during code scheduling. Register allocation is performed using a graph coloring based scheme [25]. The register allocator employs profile information, if available, to better prioritize virtual registers for allocation to physical registers. For each target architecture, a set of specially tailored peephole optimizations is performed. These peephole optimizations are designed to remove ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler," M.S. thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1993.

....27 All code generation in the IMPACT compiler is also performed using the Lcode module. Scheduling is performed via either acyclic global scheduling [29] 30] or software pipelining using modulo scheduling [31] Graph coloring based register allocation is utilized for all target architectures [32]. In addition, for each target architecture, a set of specially tailored peephole optimizations are performed. A detailed machine description database, Mdes, for the target architecture is also available to all Lcode compilation modules [33] 3.5 Architectures Supported by the Compiler Several ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler, " M.S. thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1993.

....Note that MCODE is structurally identical to LCODE and thus techniques developed in the Lcode framework can be utilized in the Mcode framework with possible machine specific extensions. Thus, at the Mcode level, machine specific optimizations, scheduling, and register allocation are performed [68]. Currently, the IMPACT compiler can generate code for the following processors: MIPS R2000, SPARC, HP PA RISC, Intel i860, AMD 29K, and Intel X86. Originally, the software pipeline scheduler was implemented in the Intel i860 code generator, 1 for two reasons. First, we can apply the software ....

R. E. Hank, "Machine independent register allocation for the impact-i c compiler." M.S. thesis, Department of Electrical Engineering, University of Illinois, Urbana, IL, 1993.

....the acyclic global scheduler. In addition to control speculation, both scheduling techniques are capable of exploiting architectural support for data speculation to achieve more aggressive schedules [16] 27] 28] Graph coloring based register allocation is utilized for all target architectures [29]. The register allocator employs execution profile information, if it is available, to make more intelligent decisions. For each target architecture, a set of specially tailored peephole optimizations is performed. These peephole optimizations are designed to remove inefficiencies during Lcode to ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler, " M.S. thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1993.

....pipelining, loops targeted for pipelining are identified at the Pcode level and marked for pipelining. These loops are scheduled using software pipelining and all other code is scheduled using the global scheduler. Graph coloring based register allocation is utilized for all target architectures [19]. The register allocator employs execution profile information if it is available to make more intelligent decisions. For each target architecture, a set of specially tailored peephole optimizations are performed. These peephole optimizations are designed to remove inefficiencies during Lcode to ....

....set of the HP PA RISC processor. The instruction latencies assumed are those of the HP PA RISC 7100 (see Table 3. 2) In order to show the full benefits or limitations of the scheduling heuristic, the code was register allocated with the IMPACT register allocator using infinite registers [19]. In addition, the execution times were generated using perfect instruction and data caches. The data cache effects will be discussed in Chapter 6. Figure 3.14 presents the speedups of issue 1, 2, 4, 8 and infinite issue scheduled using the speculative yield heuristic with the general speculation ....

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R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler," Master's thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1993.

.... technique [21] 22] or modulo scheduling [23] Both models support control and data speculation for aggressive enrichment of ILP [10] 24] 25] Register allocation, sandwiched between a prepass and a postpass schedule in the acyclic model, is performed using a graph coloring approach [26]. Since predication is introduced during the Lcode low level optimization phase and is perpetuated throughout the rest of the compiler, the predicate analysis framework is required to perform accurate analysis on Lcode and on Mcode for machines supporting predication. 2.1 Predication The ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler, " M.S. thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1995.

....thesis, all experiments utilize the IMPACT architecture. 8 The two most significant components of the code generators are the register allocator and the instruction scheduler. These modules are common to all of the code generators in IMPACT. Register allocation is performed using graph coloring [15], 2] Several different code scheduling models exist, including acyclic global scheduling [16] 17] software pipelining using modulo scheduling [18] 19] and sentinel scheduling [20] A detailed machine description database, Mdes, is referenced throughout the compilation process by various ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler, " M.S. thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1995.

....the Lcode format has facilitated the creation of several code generators for different architectures. The most actively supported architectures are the Sun SPARC, the HP PA RISC, and the Intel X86. The two main components of code generation are the instruction scheduler and the register allocator [10]. Several scheduling models exist, including acyclic global scheduling [11] 12] sentinel scheduling [13] and software pipelining using modulo scheduling [14] In addition, a scheduling technique capable of exploiting architectural support for MCB data speculation exists [2] 3] 15] The focus ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler, " Master's thesis, University of Illinois, Urbana, IL, 1993. 68

....I 4 . The check instructions are provided a slightly higher priority to push them earlier in their home block to minimize the number of instructions re executed during recovery. 3.2. 2 Register Allocator Extensions Register allocation in our compiler is done using a global graph coloring approach [9]. The register allocator assumes that all allocatable operands reside within virtual registers. For each of these virtual registers it constructs a live range which consists of the set of instructions where the operand is live. Allocation then proceeds by coloring the interference graph ....

R. E. Hank, "Machine independent register allocation for the IMPACT-I C compiler," Master's thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1993.

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Richard Hank. Machine Independent Register Allocation for the IMPACT-I C Compiler. University of Illinois at Urbana-Champaign Tech. Report. Jan, 1993.

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