B. Lin, Ch. Ykman-Couvreur, and P. Vanbekbergen, A general state graph transformation framework for asynchronous synthesis. In IMEC Technical Report, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... decisions that have significant impact on the quality of the circuit (e.g. reshuffling and insertion of state variables for state disambiguation) On another side, Petri net based techniques for synthesis are totally automatic and have been proved to be efficient for moderate size descriptions [LYCV94, LSV93] By using low level synthesis tools, logic synthesis techniques to minimize combinational and sequential circuits as well as different delay models (e.g. bounded wire delays [LSV93] or unbounded gate delays [KKL 94] can be considered for the same input specification of a circuit. ....

B. Lin, C. Ykman-Couvreur, and P. Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proc. European Design Automation Conference (EURO-DAC), pages 448--453. IEEE Computer Society Press, September 1994.

....operation that reduces the concurrency for a certain pair of transitions. The forward reduction mechanism suggested in Section 4 is a generalization of this basic operation, in that it satisfies several new correctness requirements. The method of concurrency reduction was further developed in [10] in the framework of the satisfiability approach to State Graph based asynchronous circuit synthesis, where several reductions of concurrency by pairs of transitions were performed by solving an instance of the satisfiability problem. The satisfiability approach is attractive due to its generality ....

....is attractive due to its generality (every combinatorial optimization problem can be formulated in that way) but it suffers from performance problems, and offers little control over the quality of the final solution. In particular, due to the need to reduce the solution space, the approach of [10] was limited to a smaller set of transformations than those originally described in [22] The main distinctive features of our approach with respect to [22, 10] are: 1. We use a finer reduction, by removal of State Graph arcs, than their technique based on removal of states. 2. Not every form ....

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Bill Lin, Chantal Ykman-Couvreur, and Peter Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proc. European Design Automation Conference (EURO-DAC), pages 448--453. IEEE Computer Society Press, September 1994.

....the CPU times (in seconds on a SPARCSTATION 20) required to satisfy CSC for some examples with a vast state space, which cannot be solved in a reasonable amount of memory or time by SIS or ASSASSIN. Table 2 reports the results obtained with petrify in comparison with the ones obtained by ASSASSIN ([5]) The quality of the results is comparable to those obtained by ASSASSIN. Even with the estimation of logic performed in petrify , ASSASSIN can still offer slight improvements in a few examples. This means that an estimation of logic based on only trigger signals is not accurate enough. 7 ....

Bill Lin, Chantal Ykman-Couvreur,and Peter Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proceedings of the European Design Automation Conference (EURODAC) , pages 448--453. IEEE Computer Society Press, September 1994.

....allow us to decompose state holding elements directly into stateholding elements. Since the vast majority of elements in a circuit generated by Martin synthesis are state holding, we are able to offer a much more direct implementation path. General techniques for transforming state graphs [7, 12] can also be used to solve our decomposition problem. Our solution is significantly more efficient because of its specificity to the decomposition problem. The other main contribution is our ability to test the legality of an entire parameterizable family of decompositions simultaneously. The ....

....interest, and demonstrates the utility of the proposed techniques. Full Montage style decompositions can be performed in time on the same order as the time need to perform the reachability analysis of the original system. Note that Boolean safisfiability methods for state graph transformation [12, 7] introduce new variables for each state (in this case, 32120 states) and thus do not represent a practical solution for problems of this size. Instance Type Size CPU Problem 1 S 60 0.05 S 0 4290 195 Gen 1273 4.8 Unate 522 2.8 AA 118 1.7 Problem 2 S 1138 17 S 0 164429 90328 Gen 5017 76 Unate ....

B. Lin, C. Ykman-Couvreur, and P. Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proc. EURO-DAC '94 with EURO-VHDL '94, pages 448--53, September 1994.

.... decisions that have significant impact on the quality of the circuit (e.g. reshuffling and insertion of state variables for state disambiguation) On another side, Petri net based techniques for synthesis are totally automatic and have been proved to be efficient for moderate size descriptions [14, 13]. By using lowlevel synthesis tools, logic synthesis techniques to minimize combinational and sequential circuits as well as different delay models (e.g. bounded wire delays [13] or unbounded gate delays [12] can be considered for the same input specification of a circuit. However, many designers ....

B. Lin, C. Ykman-Couvreur, and P. Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proc. European Design Automation Conference (EURO-DAC), pages 448--453. IEEE Computer Society Press, September 1994.

....were given. To combine generalized state assignment with the concurrencyreduction approachdescribed in the previous section, the Boolean constraints can be combined and solved simultaneously using any Boolean satisfiability solver. Due to space limitation, we refer the interested reader to [6] for a more extensive discussion. 5 Experimental Results All synthesis procedures described in this paper have been fully implemented in the C language. To verify these automated procedures, we have thoroughly tested them on a set of 30 realistic design examples. The results are reported in ....

B. Lin, Ch. Ykman-Couvreur, and P. Vanbekbergen, A general state graph transformation framework for asynchronous synthesis. In IMEC Technical Report, 1994.

....logic improvements up to 20 for the hazard free algorithm, and more modest improvement for the optimal critical race free algorithm. 1 Introduction There has been a renewed interest in asynchronous design, because of their potential for highperformance, modularity and avoidance of clock skew [30, 24, 14, 2, 10, 13]. This paper focuses on one class of asynchronous designs: asynchronous state machines. The design of asynchronous state machines has been an active area of research for the last 40 years (see [29] However, asynchronous state machine design remains a subtle problem, since to insure correct ....

B. Lin, C. Ykman-Couvreur, and P. Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proceedings of the 1994 European Design Automation Conference, September 1994.

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