S. Younis, Asymptotically zero energy computing using split-level charge recovery logic, Technical Report AITR-1500, MIT AI Laboratory (June 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....a better form factor than today s notebooks in regard to heat dissipation. An obvious approach to the problem of heat generation is to decrease the power required for high end CPUs through higher integration, optimized instruction sets, and more exotic techniques such as reversible computation [42]. However, profit margins, user demand, and backwards compatibility concerns are pushing industry leaders to concentrate on processors requiring more than 5 W. In addition, the explosion of mobile peripherals, such as wireless Internet radios, video cameras, sound cards, body networks, scanners, ....

S. Younis, Asymptotically zero energy computing using split-level charge recovery logic, Technical Report AITR-1500, MIT AI Laboratory (June 1994.

....a better form factor than today s notebooks in regard to heat dissipation. An obvious approach to the problem of heat generation is to decrease the power required for high end CPUs through higher integration, optimized instruction sets, and more exotic techniques such as reversible computation [45]. However, profit margins, user demand, and backwards compatibility concerns are pushing industry leaders to concentrate on processors requiring more than 5W. In ad 2 T. Starner and Y. Maguire Heat Dissipation in Wearable Computers dition, the explosion of mobile peripherals, such as wireless ....

S. Younis. Asymptotically zero energy computing using split-level charge recovery logic. Technical Report AITR-1500, MIT AI Laboratory, June 1994.

....stored in other circuit nodes, then the circuit can change state in an arbitrarily adiabatic fashion. Here, as in the study of heat engines, an adiabatic process is one that takes place without any heat flow into or out of the system. A few years ago, members of our group discovered SCRL [8, 7], a particularly simple and elegant adiabatic circuit technique that allows constructing integrated purely reversible pipelined sequential circuits using only the ordinary CMOS transitors available in commercial VLSI fabrication processes. We will describe SCRL s operation in more detail in ....

....set of four wires going back out to the neighboring processors) The wires going off the edges of the array can be folded back into the array to connect the two bit planes, or fed out to neighboring chips in a larger array. Free motion. Collision. Fig. 1. BBMCA block update rules. 3 SCRL SCRL [8, 7] has several advantages over its predecessors in adiabatic logic. The main one is that SCRL can be pipelined, allowing for continuously running, sequential adiabatic circuits. This pipelining requires that each gate that computes a function be paired with another gate to compute the inverse ....

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S. G. Younis. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. PhD thesis, MIT Artificial Intelligence Laboratory, 1994.

....of reversible computing in the long term, together with the advent of practical reversible circuit techniques, have spurred the creation of (what I call) the MIT Reversible Computing Project. This project aims to use a pipelined adiabatic circuit technique that was developed earlier in our group [14] as the basis for designing and fabricating a fully reversible, 32 bit microprocessor, called Pendulum [13] to provide a convincing proof of concept to demonstrate that designing and implementing a fully reversible architecture is not unreasonably difficult. The project will also work with other ....

....on what the best directions for further research will be. In the last few weeks, I have thought a lot about how to design a universal reversible CA that would be (1) straightforwardly implementable in SCRL (split level charge recovery logic, the adiabatic circuit technique used in our group, see [14]) 2) straightforward to implement large circuits and programs in, and (3) self modifiable so that it could dynamically reconfigure parts of its array to optimize them for different subcomputations. It might even be possible (depending on fabrication and packaging capabilities) to use I O pads ....

S. G. Younis. Asymptotically Zero Energy Computing Using SplitLevel Charge Recovery Logic. PhD thesis, MIT Artificial Intelligence Laboratory, 1994. 50

....minimum whenever a bit is erased, because bit erasure is done by dumping large numbers of electrons from a high voltage circuit node down to ground. But even this much larger energy dissipation can be avoided if the computation is done reversibly, using adiabatic circuit techniques such as SCRL [7]. The energy dissipated when bits are erased becomes a serious problem as we extrapolate current trends in computer technology to ever higher component densities and speeds. If every logic element erases a bit (namely, its previous output) on every cycle, as typically occurs in current digital ....

S. G. Younis. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. PhD thesis, MIT Artificial Intelligence Laboratory, 1994. 9

....Started Thu. Dec. 19, 1996. Revision Date: 1997 01 10 22:33:42 GMT. Formatted April 25, 1997. A current version is available at http: www.ai. mit.edu mpf rc memos M03 scrllimits.html Abstract This document explains in detail a simple analysis of the maximal energy efficiency of the SCRL [2, 1] adiabatic circuit technique when implemented using ordinary MOS devices, and of how its efficiency scales with varying threshold voltages and temperatures. The analysis is somewhat crude, and needs further development, but as a preliminary result, we find that the minimum energy per operation in ....

....per operation in SCRL circuits decreases as threshold and supply voltages increase, in contrast to standard CMOS where the opposite relation holds. 1 Brief Overview of SCRL This document is not intended to introduce the reader to SCRL. For an introduction, the reader should refer to references [2, 1]. However, for illustrative purposes, figure 1 shows an example of an SCRL gate, in this case a NAND. It can be seen that the gate consists 1 f f in out 0 in 1 H L P P L H Figure 1: A typical SCRL gate: NAND. Figure 2: SCRL pipeline. of a normal CMOS NAND structure, with the output ....

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S. G. Younis. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. PhD thesis, MIT Artificial Intelligence Laboratory, 1994.

....effectiveness of computers in severely energy limited (e.g. battery powered) contexts. However, recent developments in digital circuit design have shown that it is possible to create so called adiabatic digital circuits in which the energy per operation can actually be made as low as desired [5, 11, 12, 13, 10]. The main drawback is that individual operations must be performed more slowly. Our group is creating a general purpose CPU chip based on this technology [9] What would the applications of such a device be One context in which low energy consumption might be particularly desirable is the case ....

....discussion. 2 Reversible Adiabatic Circuits This section outlines some of the principles of operation of the circuit technology upon which our low energy computer project is based. More details can be found in the papers by Younis and Knight [11, 12, 13] and in Saed Younis s Ph.D. thesis [10]. An adiabatic electronic circuit operates dyanamically without exchanging energy with its surroundings. Although perfect adiabaticity is impossible, we can approach it as closely as desired by performing changes quasistatically, meaning in a controlled, gradual way where at any moment the system ....

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S. G. Younis. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. PhD thesis, MIT Artificial Intelligence Laboratory, 1994.

....most convenient computer to program, but it is simple, universal, reversible, and scalable. In the following sections, we note a few facts about SCRL and BBMCA, describe our circuit design and layout, and provide hand analysis indicating the power savings achieved by our circuit. 2. SCRL SCRL [1, 2] has several advantages over its predecessors in adiabatic logic. The main one is that SCRL can be pipelined, allowing for continuously running, sequential adiabatic circuits. This pipelining requires that each gate be paired with another gate to compute the reverse function. Normal SCRL stages ....

....with another gate to compute the reverse function. Normal SCRL stages cannot compute non inverting logic functions, but it is actually possible to compute noninverting functions by providing an extra pair of fast rails that split before the main rails do, and re combine after the main ones. See [1, 2]. These rails can be used to drive an extra level of logic (such as inverters) to feed the inputs of the main logicq. In this way, a single SCRL stage can compute any logic function. We used this trick to help make our circuits simpler. SCRL, along with many other adiabatic circuit families, ....

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Younis, S. G., Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic, Ph.D. Thesis, MIT Artificial Intelligence Laboratory, 1994.

....physical systems; see the examples in [14] A reversible model of computation can solve such problems more efficiently than any irreversible machine. This result is not just theoretical. In our group we have developed an electronic technology called Split Level Charge Recovery Logic (SCRL) [18, 17] that can implement arbitrary reversible operations, and in which the physical entropy generated per operation, though comparable to normal electronics when running at maximum speed, scales down as the cycle time increases. The only lower limit, due to leakage currents through nominally off ....

....of certain classes of (nonquantum) computations, a computer based on reversible primitive operations is faster than any computer that is not. Reversible computers that demonstrate this performance improvement can actually be implemented by using the SCRL circuit techniques of Younis and Knight [18, 17] together with commercially available VLSI fabrication processes. Large 3 D arrays of reversible processors of this type (perhaps several meters across) can perform physical simulations faster than any conventional computer of comparable size. Based on these insights, we have proposed a ....

S. G. Younis. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. PhD thesis, MIT Artificial Intelligence Laboratory, 1994.

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S. G. Younis. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. PhD thesis, MIT Articial Intelligence Laboratory, 1994.

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