K. Olukotun, R. Helahel, J. Levitt, and R. Ramirez, "A software /hardware co-synthesis approach to digital system simulation, " IEEE Micro., vol. 14, no. 4, pp. 48--58, Aug. 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....it reduces both the number of simulation events, and the number of simulated bits. Both reductions are effective when using an event driven hardware simulator, and only the latter is ef1 fective when using a cycle based hardware simulator. Our approach is different from those described e.g. in [9, 13, 14], that rely on a single custom simulator for hardware and software, because we can use any commercial VHDL simulator. It is also different from the class of solutions described e.g. in [11, 19, 20, 6, 21] that execute the software and hardware partitions in separate processes, keeping track of ....

K.A. Olukotun, R. Helaihel, J. Levitt, R. Ramirez "A Software-Hardware Cosynthesis Approach to Digital System Simulation" IEEE Micro, vol. 14(4):48-58, Aug. 1994.

....is done in two loops. The inner loop uses simulated annealing, with a quick estimation of the gain derived by moving an operation between hardware and software, to improve an initial partition. The outer loop uses synthesis to refine the estimates used in the inner loop. Olokutun et al. [98] perform performance driven partitioning working on a block by block basis. The specification model is a hardware description language. This allows them to use synthesis for hardware cost estimation, and profiling of a compiledcode simulator for software cost estimation. Partitioning is done ....

....FORMAL MODELS, VALIDATION, AND SYNTHESIS 381 TABLE III A COMPARISON OF PARTITIONING METHODS. Author Model Granularity Cost Function Algorithm Henkel [97] CDFG (C ) operation profiling (SW) hand (outer) synthesis and similarity (HW) simulated annealing (inner) communication cost Olokutun [98] HDL task profiling (SW) Kernighan and Lin synthesis (HW) Kumar [93] set based task profiling mathematical programming Hu [99] task list task profiling branch and bound schedule analysis Vahid [95] acyclic DFG operation profiling (SW) mixed integer linear programming processor cost (HW) ....

K. Olokutun, R. Helaihel, J. Levitt, and R. Ramirez, "A softwarehardware cosynthesis approach to digital system simulation," IEEE Micro, vol. 14, no. 4, pp. 48--58, Aug. 1994.

....system for verification and evaluation of small embedded hardware software systems generated by a hardware software cosynthesis. Fang, Wu and Yen proposed a method which supports on line debugging for logic emulation applications [8] Simulation has been also used for functional debugging [27, 40]. While the behavioral synthesis for functional debugging has not received much attention, behavioral synthesis for manufacturing testing has been extensively discussed [29, 11, 20] Register sharing is explored when register allocation is performed. Many well known register allocation algorithms ....

K.A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez, A software-hardware cosynthesis approach to digital system simulation, IEEE Micro, 14(4) (1994) 48--58.

....and schedules the processes by invoking the body function of the process in the head position of the queue. It also checks interrupts occurring between process invokes. It is only for the verification of the specification, not for the simulation of the synthesized system. l Olukotun et al. [7] partitioned systems to maximize the degree of simulation acceleration, using cosynthesis which consists of performance estimation, logic synthesis, and scheduling. After partitioning, software components and hardware components run concurrently on a compiled code based software simulator and an ....

K. A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez, " A software-hardware cosynthesis approach to digital system simulation," IEEE Micro, pp.48-58, Aug. 1994.

....Hardware and Software in a Unified Framework[7] Handling of board level module generation, System software generation, and hardware integration in a unified framework 7 Kunle A. Olukotun et al. Stanford University ) A Software Hardware Cosynthesis Approach to Digital System Simulation[8] A cosynthesis approach to digital system simulation 8 Massimiliano Chiodo et al. Magneti Marelli University of California at Berkeley Politenico di Torino ) Hardware Software Codesign of Embedded Systems[9] A formal methodology for specifying, modelling, automatically ....

....this research offers promising technology transfer from Software Engineering to Codesign. Paper No. 6 s main contribution was the handling of board level module generation, system software generation, and hardwaresoftware integration in a unified framework[7] A simulation compiler in paper No. 7[8] can receive specification written in HDL and make software hardware partitioning and scheduling based on a simulation architecture. The aim of this partitioning algorithm is speedingup the execution time of whole system. Paper No. 9 brought forward a development environment for design, ....

Kunle A. Olukotun, Rachid Helaihel, Jeremy Levitt, and Ricardo Ramirez, "A Software-Hardware Cosynthesis Approach to Digital System Simulation", in IEEE Micro, Vol. 14, No. 4, August 1994, pp. 48-58. 12

....is done in two loops. The inner loop uses simulated annealing, with a quick estimation of the gain derived by moving an operation between hardware and software, to improve an initial partition. The outer loop uses synthesis to refine the estimates used in the inner loop. Olokutun et al. OHLR94] perform performance driven partitioning working on a block by block basis. The specification model is a hardware description language. This allows them to use synthesis for hardware cost estimation, and profiling of a compiled code simulator for software cost estimation. Partitioning is done ....

....a hardware implementation. This determines some blocks which must either go into software 41 paper model granularity cost function algorithm Henkel [HEHB94] CDFG (C ) operation profiling (SW) hand (outer) synthesis and sim. anneal. similarity (HW) inner) communication cost Olokutun [OHLR94] HDL task profiling (SW) Kernighan synthesis (HW) and Lin Kumar [KAJW93] set based task profiling math. prog. Hu [HDMT94] task list task profiling branch sched. analysis and bound Vahid [VG92] acyclic DFG operation profiling (SW) Mixed processor cost (HW) Integer Linear communication cost ....

K. Olokutun, R. Helaihel, J. Levitt, and R. Ramirez. A softwarehardware cosynthesis approach to digital system simulation. IEEE Micro, 14(4):48--58, August 1994.

....overhead. Ghosh ## ##. 7] present a cosimulation environmentin which distributed cosimulation can be performed in alock step manner. Valderrama ## ##. 26] present a distributed cosimulation environment based on VCI, an automatic cosimulation interface generation tool. Olukotun ## ##. [16] obtained up to 2.76 times speedup of SW simulation using a HW simulation accelerator. In this case, communication time between the SW simulator and the HW simulation accelerator limits the cosimulation speedup. In a commercial coveri cation tool, Mentor Graphics Seamless CVE, a memory image ....

K. A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez. A Software-Hardware Cosynthesis Approach to Digital System Simulation. #### #####, pages 48-58, August 1994.

....of FPGA parts with more than ten thousand usable gates makes possible their use for programmable interfaces, fast logic emulation, and even computing elements. Section 4 has an in depth view of various uses of FPGAs. 2.2. 4 Hardware Software Codesign Hardware software codesign [Mic94, Dis93, OHLR94] concerns itself with two important questions: What aspect of a system should be done in hardware and what in software And how do we develop a complex system with hardware and software components simultaneously Research and methodologies to address the second question are often termed ....

K. A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez. A Software-Hardware Cosynthesis Approach to Digital System Simulation. IEEE Micro, 14(4):48--58, August 1994.

....control should be transferred to the hardware system, or it should be a mixed system simulator capable of simulating the hardware system and software system simultaneously. Current research in codesign does include the area of system cosimulation, and various techniques such as utilizing FPGAs [25] are used in order to speed up cosimulation. But it will be very difficult to reach a level of accuracy where the full system with caches etc. is modeled in detail and where simulation is sufficiently fast to be usable for partitioning. As mentioned above, an alternative to cosimulation is to ....

Kunle A. Olukotun, Rachid Helaihel, Jeremy Levitt, and Ricardo Ramirez. A softwarehardware cosynthesis approach to digital system simulation. IEEE Micro, 14(4):48--58, August 1994.

....[53] J.A. Rowson [93] B. Kerridge [56] Code Generation Capsys [5] Chess [58] CodeSyn [64] C. Monahan, F. Brewster [70] MOVE [36] Oscar [57] PEAS 1 [2] Analysis ADAM [48] X. Hu [37] J. Gong, et al. 29] Partitioning Cosyma [21] 34] A. Kalavade , E.A. Lee [54] K.A. Olukotun, et al. [78]; Tosca [3] Vulcan [32] 31] Case Studies GPS [102] 101] Graphics Processor [67] JPEG [30] Powertrain [37] Priority Queue [35] Spread Spectrum Receiver [26] VuMan [98] Tiger Switch [120] Achieving performance requires a careful tailoring of the system structure to the requirements ....

K. A. Olukotun et al. A software-hardware cosynthesis approach to digital system simulation. In IEEE Micro, pages 48--58, August 1994.

....(i.e. tasks mapped onto a general purpose 6 CODESIGN FOR REAL TIME VIDEO APPLICATIONS microprocessor) is addressed by many different projects on design automation. Examples include VULCAN [ 67] 66] Cosyma [ 47] Tosca [ 5] and the approaches by Kalavade [ 107] Olukotun, et al. [ 148] among others. The current version of these approaches is not suitable for designing high performance systems because a very simple target architecture is often assumed for the partitioning. In most cases this target architecture consists of a small microprocessor without memory hierarchy. A ....

....good performance is only achieved if the designer controls the parallelization [ 29] 110] Thus extending the automatic partitioning approaches to complex, high performance applications seems at least very difficult. A performance analysis based on the pixie tool is used for the software part in [ 148]. In [ 60] a code generation for VLIW processors is used to estimate the performance improvements achieved by higher degrees of instruction level parallelism. In [ 84] an analysis determines the complexity of the main tasks in a powertrain module. In [ 100] an RT level estimation technique is ....

K. A. Olukotun et al. A software-hardware cosynthesis approach to digital system simulation. In IEEE Micro, pages 48--58, August 1994.

....partitioning which is homogeneous, the partitioning in our case is heterogeneous in that some one part is implemented in software and the other part is implemented in hardware. Therefore, the latter problem is considered to be harder to solve. There have been many researches about this problem [2], 3] 4] but it is beyond the scope of this paper. We tackle the first two subproblems using the exact schedulability test of the rate monotonic scheduling algorithm [5] The rate monotonic algorithm in which a task with shorter period or with higher execution rate is assigned a higher priority ....

K. A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez, "A softwarehardware cosynthesis approach to digital system simulation," IEEE Micro, pp. 48--58, Mar. 1994.

....( n succ n k ) 3.2. Estimation The partitioner evaluates the quality of a partitioned system based on two metrics; total execution delay and total hardware cost. First, the total execution delay is estimated by a simple list scheduling algorithm, which is similar to the one proposed in [10]. For the list scheduling of hardware nodes, priority is given to a node with the largest sum of its own delay and all successors delays, thereby allowing the most critical hardware node to be scheduled first. For software nodes, priority is given to a node which has a hardware successor with the ....

K. Olukotun, R. Helaihel, J. Levitt and R. Ramirez, "A SoftwareHardware Cosynthesis Approach to Digital System Simulation," IEEE Micro, pp. 48-58, August 1994.

....have been presented for the partitioning of hardware software systems. They differ in the initial specification, the level of granularity at which partitioning is performed, the degree of automation of the partitioning process, the cost function, and the partitioning algorithm. In [23] 17] 3] [34], 38] 1] 33] automatic partitioning is 3 performed, while the approaches presented in [2] 14] 27] 10] are based on manual partitioning. Partitioning at a fine grained level is performed in [23] 17] 3] In [2] 28] 38] 1] 41] partitioning is performed at a coarser ....

....performance constraints. This differs from our approach which tries to maximize performance under given hardware and software cost constraint. The partitioning strategy presented in [28] combines a greedy algorithm with an outer loop algorithm which takes into account global measures. Similar to [34] and [41] this approach is based on exact knowledge of execution times for each task implemented in hardware or software and of all communication times. These assumptions impose hard restrictions on the features of the system specifications accepted as input. In our approach we do not necessarily ....

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K. A. Olukotun, R. Helaihel, J. Levitt, R. Ramirez, "A Software-Hardware Co-Synthesis Approach to Digital System Simulation," IEEE Micro, August 1994, pp. 48-58.

....for the partitioning of hardware software systems. They differ in the initial specification, the level of granularity at which partitioning is performed, the degree of automation of the partitioning process, the cost function, and the partitioning algorithm. In [Gupta 93, Ernst 93, Barros 94, Oluko 94] automatic partitioning is performed, while the approaches presented in [Atha 93, Edw 94, Ismail 95] are based on manual partitioning. Partitioning at a fine grained level is performed in [Gupta 93, Ernst 93, Barros 94] In [Atha 93, Kalav 94] partitioning is performed at a coarser granularity. ....

....from one approach to the other. The basic assumption is that implementing a time critical region in hardware will produce a faster execution. But other factors, such as communication cost or parallelism, can also affect dramatically the overall performance. Relatively poor results reported in [Oluko 94, Edw 94] are caused by high communication costs between the hardware and the software domains, which have not been minimized during partitioning. Iterative improvement algorithms based on neighborhood search are widely used for hardware software partitioning. In order to avoid being trapped in a ....

[Article contains additional citation context not shown here]

K.A. Olukotun, R.Helaihel, J. Levitt, R. Ramirez, A Software-Hardware Co-Synthesis Approach to Digital System Simulation, IEEE Micro, August 1994, 48-58.

....products and shorter time to market [1] There are several commercial or research prototyping systems such as RPM emulation system [1] Diodes system [2] and DSP system with multiprocessors [3] They are very expensive or limited in application and flexibility. Although simulation compiler system [4] is similar to our prototyping system, it is not oriented to rapid prototyping of system but oriented to simulation acceleration. In this paper, we propose a flexible and cost effective CAP system and some system prototyping methodologies using the system. The CAP system consists of a workstation ....

K. A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez, "A software-hardware cosynthesis approach to digital system simulation," IEEE Micro, pp. 48-58, August 1994.

....different parts of the system. To improve cosimulation performance, Thomas [4] exploits the parallelism of the (pipelined) system performing distributed dual process simulation, which gives simulation speedup when SW simulation time is greater than the simulator synchronization overhead. Olukotun [16] obtained up to 2.76 times speedup of SW simulation using a HW simulation accelerator. In this case, communication time between the SW simulator and the HW simulation accelerator limits the cosimulation speedup. In Hines s work [2] a dynamic change of communication models across levels of ....

K. A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez, "A Software-Hardware Cosynthesis Approach to Digital System Simulation", IEEE Micro, pp. 48--58, Aug. 1994.

....system for verification and evaluation of small embedded hardware software systems generated by a hardware software cosynthesis. Fang, Wu and Yen proposed a method which supports on line debugging for logic emulation applications [8] Simulation has been also used for functional debugging [27, 40]. While the behavioral synthesis for functional debugging has not received much attention, behavioral synthesis for manufacturing testing has been extensively discussed [29, 11, 20] Register sharing is explored when register allocation is performed. Many well known register allocation algorithms ....

K.A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez. A software-hardware cosynthesis approach to digital system simulation. IEEE Micro, 14(4):48--58, 1994.

....automatic generation of cosimulation interface, and (3) cosimulation speedup. Cosimulation algorithms for heterogeneous computation models, e.g. SDF, DDF, and DE, are implemented in Ptolemy environment [1] 5] and [11] present methods for automatic generation of cosimulation interface. Olukotun [7] obtained up to 2.76 times speedup of cosimulation using a hardware accelerator. In this case, communication time between software simulator and the hardware accelerator limits the cosimulation speedup. Borriello [3] suggested a dynamic change of communication models across levels of abstractions ....

K. A. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez. A software-hardware cosynthesis approach to digital system simulation. IEEE Micro, pages 48--58, August 1994.

....eight 8 bit data values. However, a 64 bit datapath limits the speedups to a factor of four or eight even though many multimedia applications have much more inherent parallelism. Computer architectures that connect a reconfigurable coprocessor to a general purpose microprocessor have been proposed [4 9]. The advantage of this approach is that the coprocessor can be reconfigured to improve the performance of a particular application. All of these proposed architectures use field programmable gate arrays (FPGAs) for the reconfigurable hardware. We refer to this coprocessor as an FPGA coprocessor ....

Kunle A. Olukotun, Rachid Helaihel, Jeremy Levitt, and Ricardo Ramirez, "A Software-Hardware Cosynthesis Approach to Digital System Simulation", IEEE Micro, Vol. 14, pp. 48--58, Nov. 1994.

....Recently, computer architectures that connect a On leave from TOSHIBA corporation, System ULSI Engineering Laboratory, 580 1 Horikawa cho Saiwai ku Kawasaki, 210, JAPAN. E MAIL: miyamori sdel.toshiba.co. jp reconfigurable coprocessor to a general purpose microprocessor have been proposed [4 10] . The advantage of this approach is that the coprocessor can be reconfigured to improve the performance of a particular application. All of these proposed architectures use field programmable gate arrays (FPGAs) for the reconfigurable hardware. The FPGA architecture, such as the small width of ....

Kunle A. Olukotun, Rachid Helaihel, Jeremy Levitt, and Ricardo Ramirez, "A SoftwareHardware Cosynthesis Approach to Digital System Simulation", IEEE Micro, Vol. 14, pp. 48--58, Nov. 1994.

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K. Olukotun, R. Helahel, J. Levitt, and R. Ramirez, "A software /hardware co-synthesis approach to digital system simulation, " IEEE Micro., vol. 14, no. 4, pp. 48--58, Aug. 1994.

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K. Olokutun, R. Helaihel, J. Levitt, and R. Ramirez. A software-hardware cosynthesis approach to digital system simulation. IEEE Micro, 14(4):48--58, August 1994.

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