M. Ward, P. Townsend and G. Watzlawik, `EDS hardware architecture', Conference on Vector and Parallel Processing,Zu rich, September 1990. Home/Search Document Not in Database Summary Related Articles Check |
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Trends in Operating Systems Towards Dynamic User-level Policy.. - Mayes (1994) (2 citations) (Correct)
....paradigm languages in a parallel environment. However, the approach to system software is very different in the two systems. 6. 1 Operating system implementation The lowest level of the EDS system software, the Primitive Machine Interface, presents an abstraction of the hardware to the kernel (Ward and Townsend, 1990). The upper 29 In such a graph reduction machine, a computational expression is represented as a graph whose nodes are packets (linear chunks of store) A packet can contain code, base values, or pointers to other packets. The pointers form the arcs of the graph. A packet has housekeeping ....
....As noted above, a virtual address space can be distributed over several nodes, using software implemented VSM. Thus, regions of the virtual address space can be shared irrespective of nodal distribution. Special hardware on each node allows copying of 128 byte sectors rather than entire 4K pages (Ward and Townsend, 1990). Thus, remote store access is supported at three levels in the EDS machine (Istavrinos and Borrmann, 1990) 1. Page copying and remote update is provided in the processor architecture. 2. Virtual memory management is provided by the kernel, including management of the address space of a ....
Ward, M. and P. Townsend (1990) EDS hardware architecture. LNCS 457, 816-827.
Data Placement in a Shared-Nothing Parallel Deductive Database - Ba Se (Correct)
....machine is a high performance parallel computer system developed as part of an ESPRIT II project. It has a homogeneous MIMD architecture with no shared memory. An extended relational database system with object oriented capabilities [11] is the main application for EDS. The EDS parallel machine [12] is based on a message passing network which provides a number of identical connection ports that can support up to 256 processing elements (PE) Each PE consists of four components: a Store Unit, a Processing Unit, a System Support Unit and a Network Interface Unit. The Store Unit has two levels. ....
M. Ward, P. Townsend, and G. Watzlawik, "EDS Hardware Architecture," CONPAR 90 - VAPP IV, Zurich, Switzerland, (September 1990).
Or-Parallel Prolog on a Distributed Memory Architecture - Silva, Watson (1997) (Correct)
....except for some novel features which are exploited by the Dorpp logic programming implementation described in the later sections of this paper. In this section we describe the EDS system, concentrating on those novel features. 2. 1 Hardware Architecture Figure 1 shows the EDS machine architecture [24]. A set of Processing Elements (PEs) are interconnected via a fast internal Delta Network. Each PE contains two SPARC CPUs, a 64MB main PE 1 2 N Delta Network Diagnostic Host Element I O Element PE PE Element . Figure 1: The EDS Machine Architecture. memory, and a Delta Network connection. ....
M. Ward, P. Townsend, and G. Watzlawik. EDS hardware architecture. In CONPAR'90, volume 457 of Lecture Notes in Computer Science, pages 816--827. Springer-Verlag, September 1990.
PARC++: A Parallel C++ - Tödter, Hammer, Struckmann (1995) (Correct)
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M. Ward, P. Townsend and G. Watzlawik, `EDS hardware architecture', Conference on Vector and Parallel Processing,Zu rich, September 1990.
.4 Simulation Results - The Simulator (Correct)
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Ward, M., Townsend, P., and Watzlawik, G. (1990). EDS hardware architecture.
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