D. Mosberger. Memory consistency models. ACM SIGOPS Operating Systems Review, 27(1):18--26, 1993. Home/Search Document Not in Database Summary Related Articles Check |
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Consistency Model Transitions in Shared Memory - Steinke (2001) (Correct)
....The original definition given by the designer of a consistency model may use notation and assumptions that are intuitively familiar to the author, but appear ambiguous to others. For example, there has been some question whether Goodman s processor consistency was intended to be stronger than PRAM [41, 45]. Later work can produce a restatement of a consistency model more intuitive to the research community at large. A common trend in the literature is the development of uniform frameworks and notation to represent models previously defined [2, 3, 7, 41] There are currently two common methods of ....
....consistency was intended to be stronger than PRAM [41, 45] Later work can produce a restatement of a consistency model more intuitive to the research community at large. A common trend in the literature is the development of uniform frameworks and notation to represent models previously defined [2, 3, 7, 41]. There are currently two common methods of characterizing consistency models. One method is to describe restrictions on the way in which processes are allowed to issue memory operations which I will call the issue method (e.g. see [3] Another method is to describe restrictions on the apparent ....
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David Mosberger. Memory consistency models. ACM SIGOPS Operating Systems Review, 27(1):18--27, January 1993.
Factors Affecting False Sharing on Page-Granularity Cache-Coherent .. - Khera (1994) (2 citations) (Correct)
....the coherency operations can be delayed and batched together to reduce overheads when it is known that a particular word will not be used by the target node during the delay. Other memory consistency models are discussed in 1 A common simplification in cache studies. 3.1. THE SIMULATOR 13 [20]. For the update memory coherency policy, another parameter limits the number of useless updates sent to a node. If a page on a node has not been used locally for a while, it is expired (marked as invalid) so future modifications to that page on other nodes will not send additional updates to ....
David Mosberger. Memory Consistency Models. ACM SIGOPS Operating Systems Review, 27(1):18--26, January 1993. See also [21] and [22].
Implementation of a New Weak Cache Coherence Protocol - Risau, Mikschl, Damm (Correct)
....of the protocol in a NUMA environment is described in detail and discussed. Keywords: weak cache coherency, sequential consistency, NUMA. e mail: Juergen.Risau informatik.uni oldenburg.de 1 Introduction Weak cache coherence protocols have been the object of extensive studies (e.g. Mos93] GLL 90] GGH91] Ste90] Egg91] ZB92] The goal almost everybody seems to have agreed upon is to provide programmers with a machine view similar to that of an uniprocessor system, namely sequential consistency. Weak coherence protocols relax this view in so far as sequential ....
....this thesis. 3 Related Work Over the years many different coherence models have evolved. In the context of multiprocessor systems they range from sequential consistency ( Lam79] over concurrent consistency ( Sch89] to release consistency ( GLL 90] and weak ordering ( DSB88] AH90] see [Mos93] for an overview of models and [AB86] for an overview of implementations of strong consistency) All of these models provide a sequentially consistent view either for all accesses (strong models) for some subset of accesses (e.g. to synchronization variables) or to all accesses provided the ....
David Mosberger. Memory consistency models. ACM SIGOP Operating Systems Review, 27(1), 1993.
A RISC Approach to Weak Cache Coherence - Risau, Mikschl, Damm (1996) (1 citation) (Correct)
....details. 1 Introduction A simple and intuitive memory model for shared memory multiprocessors is that of sequential consistency ( Lam79] However, this model severely restricts the use of many optimization techniques in multiprocessor systems ( AH90] Weak cache coherence models (see e.g. [Mos93] for an overview) often provide a restricted form of sequential consistency, namely only at certain points in time (synchronization points, e.g. in [BH90] only for a subset of memory addresses (e.g. synchronization variables, DSB88] or only if tasks adhere to certain conditions ( AH90] ....
David Mosberger. Memory consistency models. ACM SIGOP Operating Systems Review, 27(1), 1993. This article was processed using the L A T E X macro package with LLNCS style
Verifying Sequentially Consistent Memory Problem Definition - Rob Gerth (1993) (3 citations) (Correct)
....the canonical distributed memory model for a long time. In practice, however, different, still weaker memory models tend to be implemented as the synchronization overhead of SCM is still too large. For instance, the processor consistency model would allow the above behavior at the processors. See [Mos93] for an overview of distributed memory models. A formal definition Let Delta j i denote the operation on behaviors of removing the events that do not originate from process P i or that are not external. Then we have A memory M is sequentially consistent w.r.t. M serial , M s:c: M serial , iff ....
D. Mosberger. Memory consistency models. ACM SIGOP Operating Systems Review, 27(1):18--27, 1993.
The DSS, a Middleware Library for Efficient and.. - Klintskog, Banna.. (Correct)
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D. Mosberger. Memory consistency models. ACM SIGOPS Operating Systems Review, 27(1):18--26, 1993.
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