Ed Harcourt, Jon Mauney, and Todd Cook. Specification and simulation of instruction-level parallelism. In Proceedings of NAPAW'93, the North American Process Algebra Workshop, 1993. Home/Search Document Not in Database Summary Related Articles |
This paper is cited in the following contexts:
High-Level Timing Specification of Instruction-Level.. - Harcourt, Mauney, Cook (1993) (2 citations) Self-citation (Harcourt Mauney Cook) (Correct)
....properties of the instructions are often visible to the user of the processor. Consequently, such properties should be included in any behavioral processor specification. We present a technique for formally describing, at a high level, the timing properties of pipelined, superscalar processors [PH90, Joh91, HMC93]. We illustrate the technique by specifying and simulating a hypothetical processor that includes many features of commercial processors including delayed loads and branches, interlocked floating point instructions, and multiple instruction issue. As our mathematical formalism we use SCCS, a ....
Ed Harcourt, Jon Mauney, and Todd Cook. Specification and simulation of instruction-level parallelism. In Proceedings of NAPAW'93, the North American Process Algebra Workshop, 1993.
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