Ingrid Verbauwhede, Frank Hoornaert, Joos Vandewalle and Hugo de Man, Security and Performance Optimization of a New DES Data Encryption Chip , IEEE Journal of Solid State Circuits Vol. 23, No. 3, pp. 647-656, June 1988  Home/Search   Document Details and Download   Summary   Related Articles   Check

....9: Computation Farm Block Diagram 4 System Level Parallelism To maintain constant throughput rates requires careful consideration of the encryption system s interface or input output section. Overlap of the input, output and encryption processes of subsequent text blocks provides high throughput [Ver88]. Similarly, DMA support decouples the host processor from the encryption function to allow CPU processing of other tasks to proceed in parallel with the encryption request[Anderson87] 5 Conclusion Parallel aspects of the DES may be exploited at three levels: within the algorithm kernel, through ....

Ingrid Verbauwhede, Frank Hoornaert, Joos Vandewalle and Hugo de Man, Security and Performance Optimization of a New DES Data Encryption Chip , IEEE Journal of Solid State Circuits Vol. 23, No. 3, pp. 647-656, June 1988

....however require such high throughputs for the encryption decryption process that they cannot be executed on a normal general purpose microprocessor. These applications require dedicated ASIC implementations. A number of hardware implementations for cryptographic algorithms have been realized [6, 7, 8, 9, 10, 11]. These implementations allow for higher throughputs than if the algorithms would be executed in software on a general purpose processor. e.g. 6] 14.2 Mbit sec, 7] 4.7 Mbit sec, 8] 20 Mbit sec (1:5 m CMOS) 9] 30 Mbit sec (2:4 m CMOS at 24 MHz) 11] 44.1 Mbit sec (1:5 m CMOS at 25 MHz) ....

....implementations for cryptographic algorithms have been realized [6, 7, 8, 9, 10, 11] These implementations allow for higher throughputs than if the algorithms would be executed in software on a general purpose processor. e.g. 6] 14.2 Mbit sec, 7] 4. 7 Mbit sec, 8] 20 Mbit sec (1:5 m CMOS) [9]: 30 Mbit sec (2:4 m CMOS at 24 MHz) 11] 44.1 Mbit sec (1:5 m CMOS at 25 MHz) Some of these processors implement the DES [5] algorithm [9, 10] All of these ASIC implementations are limited to medium throughput applications. High speed applications such as digital real time video (e.g. pay ....

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I. Verbauwhede, e.a., "Security and Performance Optimization of a new DES Data Encryption Chip",IEEE JSSC, Vol. 23, No.3, pp. 647656, June 1988.

....[27] 0.60 m 200M 2 , 500 ns biquad 0.010 0.010 FPGA XC4K [26] 0.60 m 60 CLBs, 320 ns biquad 0.044 43 CLBs, 200 ns biquad 0.093 Full Custom [16] 0.90 m 68M 2 , 11.8 ns 4 biquads 5. 0 Table 3: IIR Throughput Comparison Architecture Reference Feature Area Keys Second Size ( Keys 2 s DES IC [35] 1.5 m 11.1M 2 310K 0.028 FPGA Altera 8K [13] 0.30 m 81188 (930M 2 ) 800K 0.00086 RISC [32] 13] 0.30 m 1.8G 2 41K 0.000023 Table 4: DES Key Search their processor area; this, too, may be optimistic since the first SPARCs had no on chip data caches and even the SuperSparc cache is too small ....

....in time for low volume, board level component consumers, but will not remain stable or accurate across shifts in component supply and demand. Preliminary Copy Contact author amd cs.berkeley.edu for final. Architecture Reference Feature Area Time Block Size ( blocks 2 s DES IC Custom [35] 1.5 m 11.1M 2 3,200 ns 0.028 DES IC Std. Cell [23] 0.50 m 344M 2 640 ns 0.0045 FPGA XC3K [34] 0.60 m 3 XC3090s = 1.25G 2 3,800 ns 0.00021 RISC [10] 30] 0.38 m 1.7G 2 34,500 ns 0.000017 # Xilinx # Full Custom # Std. Cell # RISC 1 10 100 ....

Ingrid Verbauwhede, Frank Hoornaert, Joos Vandewalle, and Hugo J. De Man. Security and Performance Optimization of a New DES Data Encryption Chip. IEEE Journal of Solid-State Circuits, 23(3):647--656, June 1988.

....algorithm kernel, and in the encryption processor I O design. Maintaining constant throughput rates requires careful consideration of the encryption system s interface or input output section. Overlap of the input, output and encryption processes of subsequent text blocks provides high throughput [23] Similarly, DMA support decouples the host processor from the encryption function to allow CPU processing of other tasks to proceed in parallel with the encryption request [2] We developed a DES board [3] using SSI TTL and MSI PALs using the MUX key register approach. Testing of a wirewrapped ....

Ingrid Verbauwhede, Frank Hoornaert, Joos Vandewalle, and Hugo de Man, "Security and Performance Optimization of a New DES Data Encryption Chip," IEEE Journal of Solid State Circuits 23(3), pp. 647-656 (June 1988).

....not the wiring of the critical path, the iteration feedback loop. Figure 10 shows one DES iteration. The wires belonging to the critical path are highlighted. This feedback loop contains two permuted data paths: permutations E and P. While other implementations have chosen a register sliced layout [9, 18], I preferred a mixed strategy. As shown in Figure 11, I first divide the design into blocks corresponding to the eight S boxes. I further subdivide each block into four bit slices each containing one bit of the left and the right half of registers I, I , I , LR, and O. The register bits are laid ....

I. Verbauwhede, F. Hoornaert, J. Vandewalle, H. De Man, Security and Performance Optimization of a New DES Data Encryption Chip. IEEE Journal of Solid-State Circuits, Vol. 23, No. 3, June 1988, pp. 647-656.

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I. Verbauwhede, F. Hoornaert, J. Vandewalle, and H. J. De Man, "Security and performance optimization of a new des data encryption chip," IEEE Journal of Solid-State Circuits 23, pp. 647--656, June 1988.

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