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Kevin O'Brien, Bill Hay, Joanne Minish, Hartmann Schaffer, Bob Schloss, Arvin Shepherd, and Matthew Zaleski. Advanced compiler technology for the RISC System/6000 architecture. In IBM RISC System/6000 Technology. IBM Corporation, Armonk, New York, 1990.

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Effective Partial Redundancy Elimination - Briggs, Cooper (1994)   (33 citations)  (Correct)

....subexpressions into loop variant and loop invariant parts, hoisting the invariant parts. We presume their approach is a development of earlier work within IBM. Other work by O Brien et al. and Santhanam briefly describe what are apparently further developments of the Cocke and Markstein approach [22, 24]. It is difficult to compare our approach directly to these earlier methods. We were motivated by a desire to separate concerns. We already had solutions to hoisting loop invariants and strength reduction; therefore, we looked for a way to reassociate expressions. We also prefer our global ....

Kevin O'Brien, Bill Hay, Joanne Minish, Hartmann Schaffer, Bob Schloss, Arvin Shepherd, and Matthew Zaleski. Advanced compiler technology for the RISC System/6000 architecture. In IBM RISC System/6000 Technology. IBM Corporation, Armonk, New York, 1990.


Improving the Performance of Cache Memories Without Increasing.. - Carter   (Correct)

....to produce extremely effective code for the hardware. The RISC System 6000 s compilers perform several optimizations that are specifically tailored to the configuration of the hardware, in addition to more traditional optimizations such as common subexpression elimination and register allocation [8]. Once the preliminary code generation section of the compiler has determined which instructions need to be executed to produce the correct output, the compiler re orders these instructions to increase the efficiency with which they can be dispatched to the execution units, while ensuring that the ....

Kevin O'Brien, Bill Hay, Joanne Minish, Hartmann Schaffer, Bob Schloss, Arvin Shepherd, and Matthew Zaleski. Advanced compiler technology for the RISC System/6000 architecture. In IBM RISC System/6000 Technology, pages 154--161. IBM Corporation, 1990.


The Multiflow Trace Scheduling Compiler - Lowney, Freudenberger, Karzes.. (1992)   (154 citations)  (Correct)

....are performed before the first unrolling; this permits us to have an accurate estimate of loops size for our heuristics. After the first unrolling, the induction variables are rewritten, and optimization is performed across the unrolled bodies (achieving the effect of predictive commoning [55]) Both induction variable simplification and commoning across loop bodies may increase register pressure. By keeping the first unrolling small, we prevent the register pressure in the loop from exceeding the available registers. We also keep the constant displacements introduced by the induction ....

....binding is propagated to the exit VLM. Figure 9 16: Resolution of a delayed binding 10 Instruction scheduler Our instruction scheduler transforms a trace of IL2 operations into a schedule of wide instructions; it encompasses both the scheduling and register allocation phases of other compilers [16, 32, 34, 17, 18, 56, 31, 55, 72, 11, 12]. The operations have been lowered to machine level by Phase2. For each operation, the instruction scheduler must assign registers for the operands, assign a functional unit for the operation, and place the operation in a wide instruction. It performs a three step algorithm. A. Build a data ....

[Article contains additional citation context not shown here]

O'Brien, Kevin, Bill Hay, Joanne Minish, Hartmann Schaffer, Bob Schloss, Arvin Shepherd, Mathew Zaleski, Advanced Compiler Technology for the RISC System/6000 Architecture. IBM RISC System/6000 Technology, IBM, 1990, pp. 154-161.


Path-Sensitive Value-Flow Analysis - Bodik, Anik (1998)   (11 citations)  (Correct)

.... a version of PRE that is more powerful than the best existing algorithms [30, 40] By using names created through back substitution across multiple loop iterations, VNGPRE subsumes predictive commoning, an optimization aimed at removing common subexpressions recurring across loop iterations [26, 34]. VNG is also being used to carry out PRE of load store operations; it is worth noting that the popular (cf. 26] algorithm in [11] computes 11 data flow problems, while the VNG is able to subsume this optimization by solving only three problems. We are currently considering the use of VNG for ....

K. O'Brien, B. Hay, J. Minish, H. Schaffer, B. Schloss, A. Shepherd, and M. Zaleski. Advanced Compiler Technology for the RISC System/6000 Architecture. IBM Corporation, 1991.


XIL and YIL: The Intermediate Languages of TOBEY - Brien, O'Brien, Hopkins.. (1995)   (4 citations)  Self-citation (O'brien)   (Correct)

.... compilers share a common back end, the Toronto Optimizing Back End with Yorktown, TOBEY, which was inspired by an earlier compiler project for the 801 minicomputer, the pl.8 compiler, and XIL owes several of its major features to the intermediate language of that compiler [16] The TOBEY optimizer [15] utilizes familiar techniques such as Common Subexpression Elimination (CSE) upward motion of invariant computations from loops, elimination of dead or unused expressions, and Strength Reduction and Reassociation. A host of other transformations are performed, namely, global constant propagation, ....

....that YIL was designed for, it also requires a more detailed representation of the operations of the machine. Fortuitously, the fact that XIL is embedded in YIL allows for the required level of detail. A further example of the useful co existence of XIL and YIL is the predictive commoning [15] optimization of TOBEY. While initially prototyped in XIL with some degree of success, it was felt that this optimization could be more optimistic when applied at the level of YIL. Consider the following loop: DO i = 2; 100 a(i) b(i Gamma 1) b(i) b(i 1) END DO Notice that the ....

O'Brien,J.K. et al Advanced Compiler Technology for the RISC System/6000 Architecture In IBM RISC System/6000 Technology, SA23-2619, IBM Corporation.


Path-Sensitive Value-Flow Optimizations - Bodík (1998)   (Correct)

No context found.

K. O'Brien, B. Hay, J. Minish, H. Schaffer, B. Schloss, A. Shepherd, and M. Zaleski. Advanced Compiler Technology for the RISC System/6000 Architecture. IBM Corporation, 1991.


Register Allocation with Instruction Scheduling: a New Approach - Pinter (1993)   (67 citations)  (Correct)

No context found.

K. O'Brien, B. Hay, J. Minish, H. Schaffer, B. Schloss, A. Shepherd, and M. Zaleski. Advanced compiler technology for the RISC System/6000 architecture. In IBM RISC System/6000 Technology, pages 154--161. IBM SA23--2619, 1990.

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