Kannan Narasimhan and Kelvin D. Nilsen. Portable execution time analysis for RISC pro87 cessors. In ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems, June 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....all possible paths in the control flow graph. However, our graph based approach uses a heuristic [1] with a good trade off between accuracy and computation time consumption. Most publications on LLA concentrate on only one of the aspects caching or pipelining separately, e.g. 15] on caching or [16] on pipelining. Our approach integrates both aspects by using the results of the caching analysis for the pipelining analysis ( 21] 3. Design Flow In this section we give an overview of how a parallel embedded real time system is modeled following our design methodology (see Figure 1) The ....

K. Narasimhan and K. D. Nilsen. Portable Execution Time Analysis for RISC-Processors. In ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems. ACM, 1994.

....paths. Zhang in [ZBN93] uses a modelbased basic block approach that predicts worst case execution times of programs on the Intel 80C188 architecture. A micro code analysis technique that predicts optimistic execution times of code segments for simple pipelined processors is presented in [HBW94] [NN94] describes a tool that generates an execution time analyzer for RISC processors. Wang in [Wan94] presents a framework for predicting performance of code transformations that may be performed during compiler optimization. In [CH95] Chandra and Harmon model processor resources such as pipelines and ....

K. Narasimhan and K. D. Nilsen, "Portable Execution Time Analysis for RISC Processors", Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tool Support for Real-Time Systems, June, 1994.

....blocks. The handling of data caches is only briefly mentioned in this paper. The WCTAs are comparable to the pipeline modelling used in PTA. However, they are more storage intensive and less accurate than the data structures of PTA. The prediction of pipeline performance is discussed in [5] and [13]. There the pipeline behaviour is simulated for a given code segment. 13] introduces the pipeline simulator compiler psc, which uses a description of a processor to generate a program that simulates the execution of code on this processor. The main shortcoming of these approaches is that they ....

....The WCTAs are comparable to the pipeline modelling used in PTA. However, they are more storage intensive and less accurate than the data structures of PTA. The prediction of pipeline performance is discussed in [5] and [13] There the pipeline behaviour is simulated for a given code segment. [13] introduces the pipeline simulator compiler psc, which uses a description of a processor to generate a program that simulates the execution of code on this processor. The main shortcoming of these approaches is that they do not take into account the cache performance. So each memory reference ....

Kannan Narasimhan, Kelvin D. Nilsen. "Portable Execution Time Analysis for RISC-Processors". ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, June 1994.

....a RISC processor, however, the calculation of a tight WCET bound of a program involves difficulties that come from the very characteristics of RISC processors: pipelined execution and instruction data caching. Recently there has been much progress in worst case timing analysis for RISC processors [2, 5, 7, 10, 11, 13, 14]. However, most of the previous studies focused mainly on the timing analysis of pipelined execution and instruction caching, while largely ignoring the data caching effects [2, 5, 10, 13, 14] Even the approaches that do consider the timing effects of data caching have severe restrictions. For ....

....caching. Recently there has been much progress in worst case timing analysis for RISC processors [2, 5, 7, 10, 11, 13, 14] However, most of the previous studies focused mainly on the timing analysis of pipelined execution and instruction caching, while largely ignoring the data caching effects [2, 5, 10, 13, 14]. Even the approaches that do consider the timing effects of data caching have severe restrictions. For example, the technique explained in [11] requires that the addresses of references from each program construct be fixed. For instruction block 1 references, such a requirement is satisfied for ....

K. Narasimhan and K. D. Nilsen. Portable Execution Time Analysis for RISC Processors. In Proceedings of the Workshop on Architectures for Real-Time Applications, April 1994.

....a timing estimation for real time systems since their predictions are usually not guaranteed, or enormous cost is needed. Because of these limitations of the measurementbased approaches, analytical approaches are becoming more popular. There have been several recent studies about this issue [4, 8, 9, 18, 19, 20, 22, 23, 24, 27, 28]. In many of these studies, the assumed machine model is a simple non pipelined processor without cache memory [18, 22, 23, 27] Thus the timing effects of pipelined execution and cache memory are not taken into account. 2.1 Timing analysis of pipelined execution The timing effects of pipelined ....

....Thus the timing effects of pipelined execution and cache memory are not taken into account. 2. 1 Timing analysis of pipelined execution The timing effects of pipelined execution have been recently studied by Harmon, Baker, and Whalley [9] Harcourt, Mauney, and Cook [8] Narasimhan and Nilsen [20], and Choi, Lee, and Kang [4] In these studies, the execution time of a sequence of instructions is estimated by modeling a pipelined processor as a set of resources and representing each instruction as a process that acquires and consumes a subset of resources in time. In order to mechanize the ....

[Article contains additional citation context not shown here]

K. Narasimhan and K. D. Nilsen. Portable Execution Time Analysis for RISC Processors. In Proceedings of the Workshop on Architectures for Real-Time Applications, April 1994.

....used to obtain such bounds. Measurement based techniques are, in many cases, inadequate to produce a timing estimation for real time systems since their predictions are usually not guaranteed, or enormous cost is needed. Due to these limitations, analytical approaches are becoming more popular [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]. Many of these analytical studies, however, consider a simple machine model, thus largely ignoring the timing effects of pipelined execution and cache memory [8, 12, 13, 15] A. Timing Analysis of Pipelined Execution The timing effects of pipelined execution have been recently studied by Harmon, ....

....thus largely ignoring the timing effects of pipelined execution and cache memory [8, 12, 13, 15] A. Timing Analysis of Pipelined Execution The timing effects of pipelined execution have been recently studied by Harmon, Baker, and Whalley [6] Harcourt, Mauney, and Cook [5] Narasimhan and Nilsen [11], and Choi, Lee, and Kang [4] In these studies, the execution time of a sequence of instructions is estimated by modeling a pipelined processor as a set of resources and representing each instruction as a process that acquires and consumes a subset of the resources in time. In order to ....

[Article contains additional citation context not shown here]

K. Narasimhan and K. D. Nilsen, "Portable Execution Time Analysis for RISC Processors," in Proceedings of the Workshop on Architectures for Real-Time Applications, April 1994.

....cycle. There are several types of hazards that cause to stall the pipeline [2] In a RISC processor, the WCET of each instruction depends on its interactions with other instructions in the pipeline. Some of issues that we consider when calculating the WCETs of instructions within a basic block are [5]: 1. The stage in the pipeline where the source operands are required. 2. The stage in the pipeline where the result is ready. 3. The resources required at each step of the instruction s execution. 3.2 Architecture Description The input to the RTAG is an architecture description that accounts ....

K. Narasimhan, K. Nilsen, "Portable execution time analysis for RISC Processors," unpublished technical report, 1994

....the effect of pipelined execution through the pattern matching scheme. Zhang and Burns and Nicholson [45] developed a mathematical model of a two stage pipelined processor and a method based on this model to calculate the WCET of a program that executes on this processor. Narasimhan and Nilsen [32] developed a tool that takes as input an architecture description file of a RISC processor and produces as output a timing analyzer. The analyzer accounts for the effect of pipelining on the RISC processor when predicting the WCET. Several approaches integrate the timing analysis of instruction ....

Kannan Narasimhan and Kelvin D. Nilsen. Portable execution time analysis for RISC pro87 cessors. In ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems, June 1994.

....an execution time analyzer for any RISC processor. It takes structural, control, and data hazards into account. One of the major shortcomings of all existing execution time analyzers is that they are machine dependent. This is a serious problem because machine architectures evolve rapidly [NN94]. The interesting thing with this approach is that you give an Architecture Description File (adf) to the psc tool, and gets an execution time analyzer as output. This means that you do not have to write a new tool, when a new RISC processor is released. You just have to fix a new architecture ....

....Architecture Description File (adf) to the psc tool, and gets an execution time analyzer as output. This means that you do not have to write a new tool, when a new RISC processor is released. You just have to fix a new architecture description file (input file) The adf consists of four sections [NN94]: 1. Macro Definition Section 2. Resource Definition Section 3. Instruction Definition Section 4. Assembly Syntax Section The first, second and third section, are used to model the target architecture. The fourth section is used to describe a parser for the targets assembly language . The ....

K. Narasimhan and K. D. Nilsen. Portable Execution Time Analysis for RISC Processors. Technical report, Department of Computer Science, Iowa State University, 1994.

....blocks. The handling of data caches is only briefly mentioned in this paper. The WCTAs are comparable to the pipeline modelling used in PTA. However, they are more storage intensive and less accurate than the data structures of PTA. The prediction of pipeline performance is discussed in [14] and [30]. There the pipeline behaviour is simulated for a given code segment. 30] introduces the pipeline simulator compiler psc, which uses a description of a processor to generate a program that simulates the execution of code on this processor. The main shortcoming of these approaches is that the ....

....The WCTAs are comparable to the pipeline modelling used in PTA. However, they are more storage intensive and less accurate than the data structures of PTA. The prediction of pipeline performance is discussed in [14] and [30] There the pipeline behaviour is simulated for a given code segment. [30] introduces the pipeline simulator compiler psc, which uses a description of a processor to generate a program that simulates the execution of code on this processor. The main shortcoming of these approaches is that the cache performance is not taken into account. So each memory reference must ....

Kannan Narasimhan, Kelvin D. Nilsen. "Portable Execution Time Analysis for RISC-Processors". ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, June 1994.

....RMA. Lower priority tasks also execute within their deadlines because for each preemption that might occur, the high priority preempting task has left#idle# enough time to restore the cache to its original state. C may be calculated by any variety of established methods or combination of methods[15,16,17,18]. As regards g, a first approximation for bounding g is to assume that it is the cost to completely fill the cache: this is approximately 500 s on current processors. However, it is possible to obtain tighter bounds. Clearly, an upper bound on cache interference caused by a pre empting task is ....

Narasimhan, K. & Nilsen, K: #Portable Execution Time Analysis for RISC Processors#. Proceedings of the Workshop on Architectures for Real--Time Applications, International Symposium on Computer Architectures, Chicago, April 1994

....utilization will be less than 10 . This is unacceptable in high volume mass marketed computer systems. 3. Pipeline Simulation In order to accurately account for the benefits of pipelined instruction execution, we have designed and implemented a pipeline simulator compiler, which we call psc [14]. psc takes as input a structured description of a target machine architecture and produces as output a program which is capable of simulating the target machine s pipelines. The psc generated pipeline simulator accounts for structural, control, and data hazards. The pipeline simulator accounts ....

K. Narasimhan and K. Nilsen, Portable Execution Time Analysis for RISC Processors, ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, June 1994.

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Kannan Narasimhan and Kelvin D. Nilsen. Portable execution time analysis for RISC pro87 cessors. In ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems, June 1994.

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