R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham, "VLSI Logic and Fault Simulation on General-Purpose Parallel Computers," IEEE Trans. on ComputerAided Design, Vol. 12, No. 3, pp. 446-460, March 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....loops need to be removed by ignoring some arcs. An improved technique based on cone partitioning for synchronous algorithms allows the redundant evaluation of gates in different processors. It assigns each cone independently and uses a DFS technique to reduce the 19 interprocessor communication [74]. Random and string partitioning have approximately 10 percent more concurrency than the cone partitioning strategy does [89] The problem of workload minimization of overlapping tasks was discussed in the parallel compiled event driven simulation of a VHDL model in [60] However, the scalability ....

....capturing the global graph structure is important for large graphs. However, their work only considers minimizing the edge cut of a graph. 21 2. 4 PDES Performance Parallelization of sequential logic simulations [9] has been performed using techniques ranging from synchronous parallel simulation [74] to asynchronous optimistic simulation [3, 7, 18, 23] Basically, synchronous simulations are performed by synchronizing events with the same timestamp. Synchronous algorithms using a global clock have not achieved reasonable speedup due to the excessive computational load of global ....

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R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham, "VLSI Logic and Fault Simulation on General-Purpose Parallel Computers," IEEE Trans. on ComputerAided Design, Vol. 12, No. 3, pp. 446-460, March 1993.

....of a following simulation. Starting from ideas of D.Zike and W.Roesner presented in [3] we have developed a hierarchical partitioning strategy outlined in [4] based on fan in cones as elementary building blocks for partitions. Related work to cone based partitioning can be found in [5] and [6]. Within the taxonomy of partitioning techniques given in [7] our strategy embodies a bottom up clustering approach. Partitioning algorithms regarded at the end of this paper follow a special two stage strategy, where Evolutionary Algorithms are applied after a fast pre partitioning phase which ....

....the above partition valuation method into our two level partitioning scheme outlined in [4] At the rst level fast pre partitioning algorithms are applied to reduce problem complexity by concentrating cones into super cones. Here we consider the algorithm of Mueller Thuns et al. MT ) described in [6] and our STEP algorithm. Both algorithms yield partitions which are balanced with respect to the number of cones within the partition components. There is no explicit partition valuation at the rst level of our scheme. At the second level, Evolutionary Algorithms (EAs) are applied starting with an ....

R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham, VLSI logic and fault simulation on general purpose parallel computers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 12(3), 1993, 446{ 460.

....strategy is introduced in [4] followed by a special instance called mixture of experts approach described in [5] Based on ideas of D.Zike and W.Roesner presented in [8] we consider fan in cones as elementary components for building model partitions. Related work is reported in [6] and [7]. The model partitioning problem can be formulated as a combinational optimization problem. In this context partitions are related to quantities (costs) which more or less directly express a connection to parallel simulation run time (partition valuation) For partition valuation a model of ....

R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham. VLSI logic and fault simulation on general purpose parallel computers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, pages 446-460, 1993.

....directly in uences model partitioning. Assigning a logical element to a model part requires the same assignment for all logical elements of the whole model which are able to contribute to a change of an input value of the considered element during one cycle. If special fan in cones [SUM87, Man92, MTSDA93] are taken as basic building blocks for model partitioning, the demand mentioned above is ful lled. A model partition is directly related to certain workloads of the processors involved in later parallel simulation and communication overhead between co operating TEXSIM instances. In this way ....

....hardware. Due to our parallelization approach, cutting signals of M S during a partitioning of M is only permitted at cycle boundaries related to the clock cycle algorithm mentioned above. Therefore, we are forced to de ne basic units for partitioning which are known as cones [SUM87, Man92, MTSDA93] These units comprise elements of MB with a limiting head element out of MO [ M L . For further investigations of the partitioning problem we x the following formal de nitions with respect to an arbitrarily chosen hardware model M : De nition 2 The fan in cone co I (x) of an element x 2 ....

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R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham. VLSI Logic and Fault Simulation on General Purpose Parallel Computers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12:446-460, 1993.

....parallel circuit simulation: synchronous, conservative asynchronous, and optimistic asynchronous. Synchronous techniques attempt to execute events with the same timestamp in parallel. Although some performance benefits have been reported with synchronous and loosely synchronous parallel simulation [20, 24, 25], other studies have shown that these techniques do not appear to scale. Wong et al. 30] reported that in small circuits, ranging from 347 to 3,680 elements, the average activity level was only about 1.2 and the average concurrency level (i.e. average number of simultaneous events) was of ....

....the hierarchical information is displayed as shown in Figure 6, where circles represent leaf nodes and rectangles represent higher level functional blocks. Two heuristics were used to partition the circuits simulated by MIRSIM: ffl Partition on the boundary of clocked latches. Mueller Thuns et al. [13, 25] have suggested that sequential circuits can be partitioned on the boundaries of clocked latches. Therefore, messages are released at the clock rate which will reduce the communication overhead. ffl Avoid partition induced cycles. For example, the gate s comp can be partitioned either with ....

R.B. Mueller-Thuns, D.G. Saab, R.F. Damiano, and J.A. Abraham. VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, 12(3):446--460, March 1993.

....algorithms. These results are presented in Figure 1. Note that there are a large number of differences between these implementations, including different abstraction levels, timing models, example circuits, execution platforms, and implementors (e.g. Briner et al. 10] Mueller Thuns et al. [21], Soule and Gupta [26] Sporrer and Bauer [27] and Su and Seitz [29] This limits the ability to draw firm conclusions; however, a number of trends are evident. First, none of the conservative asynchronous implementations reported good performance, while a number of synchronous and optimistic ....

R.B. Mueller-Thuns, D.G. Saab, R.F. Damiano, and J.A. Abraham. VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 12(3):446--460, March 1993.

....1 Introduction Fault simulation at the logic gate level is an important component of the design process in digital systems. Practical experience has indicated that the computational effort involved in fault simulation is very large. Parallel processing is one method to reduce compute time [1, 2]. A simulation algorithm can be parallelized using algorithm (task) parallelism[1, 3] model parallelism[2, 4 6] data parallelism [4, 7] or a combination of these techniques [4] In a data parallel algorithm, the data to be simulated are partitioned into disjoint sets and each set assigned to a ....

....in digital systems. Practical experience has indicated that the computational effort involved in fault simulation is very large. Parallel processing is one method to reduce compute time [1, 2] A simulation algorithm can be parallelized using algorithm (task) parallelism[1, 3] model parallelism[2, 4 6], data parallelism [4, 7] or a combination of these techniques [4] In a data parallel algorithm, the data to be simulated are partitioned into disjoint sets and each set assigned to a processor. Each processor executes the entire simulation algorithm and simulates the entire circuit. In parallel ....

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R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham, "VLSI logic and fault simulation on general-purpose parallel computers," IEEE Transactions on Computer-Aided Design, pp. 446--460, March 1993.

....parallel circuit simulation: synchronous, conservative asynchronous, and optimistic asynchronous. Synchronous techniques attempt to execute events with the same timestamp in parallel. Although some performance benefits have been reported with synchronous and loosely synchronous parallel simulation [12, 14, 15], other studies have shown that these techniques do not appear to scale. Wong et al. 20] reported that in small circuits, ranging from 347 to 3,680 elements, the average activity level was only about 1.2 and the average concurrency level (i.e. average 1 Copyright 1997 IEEE. Published in the ....

....number of transistors in each partition, and communication topology to evaluate the quality of the partitioning. 4.1 Manual partitioning A designer can use the circuit s structure information to produce a balanced partition with low communication overhead. For example, Mueller Thuns et al. [8, 15] have suggested that sequential circuits can be partitioned on the boundaries of clocked latches in order to reduce the communication overhead. However, it is very difficult to recognize latches in a flat transistor netlist. To solve this problem, MIRSIM provides an interactive GUI, called ....

R.B. Mueller-Thuns, D.G. Saab, R.F. Damiano, and J.A. Abraham. VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12(3):446--460, March 1993.

.... [1] Parallel processing is one method to reduce simulation time and costs [2] In general, the gains from parallelism have been limited and drop off sharply as the number of processors is increased [6] To analyze performance, models have been developed to characterize computational activity [3, 4]. They show that the distribution of activity impacts parallel performance. The contribution of this paper is a characterization of the computational activity in gate level fault simulation. As in logic simulation, computational activity varies significantly across the circuit. However, the ....

....distribution in fault simulation is discussed in Section 3. We conclude with a summary of our results in Section 4. 2 Preliminaries In a real circuit, the internal signal changes caused by primary input changes do not occur sequentially. Given this inherent parallelism, parallel processing [4] [8] should be an attractive option. In practice, the gains have been limited. Initially, performance improves as the number of processors is increased. However, the gains diminish as the number of processors increases. Performance gains with massively parallel systems are especially limited [2, ....

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R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham, "VLSI logic and fault simulation on general-purpose parallel computers," IEEE Transactions on Computer-Aided Design, pp. 446--460, March 1993.

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