David A. Wood, Susan Eggers, and Garth Gibson. SPUR memory system architecture. Technical Report UCB/CSD 87/395, University of California, Berkeley, December 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....network, as shown in Figure 2.1. A variety of communication networks and memory system architectures were used by these machines, but their defining characteristic is that all memories are equally distant from all processors. Bus based shared memory systems, such as the Berkeley SPUR machine [38], and the Firefly workstation [37] are an important subclass of centralized shared memory systems, in which processors communicate with the centralized memory system over a shared memory bus. This architecture maintains cache coherence by having the memory controller for each processor examine ....

David A. Wood, Susan Eggers, and Garth Gibson. SPUR memory system architecture. Technical Report UCB/CSD 87/395, University of California, Berkeley, December 1987.

....item through different virtual addresses causes that item to appear simultaneously in multiple cache lines, creating a coherency problem on writes. Many solutions to this problem have been devised, such as allocation restrictions (as in Sun OS [Cheng 87] sharing on segment boundaries only (SPUR [Wood et al. 87] and the IBM RISC processors [Chang Mergen 88, Groves Oehler 90] flushing the cache on process switches (as required by the i860 [Int 89] lazily flushing aliased pages from the cache [Wheeler Bershad 92] or hardware support for synonyms [Goodman 87, Wang et al. 89] The first two ....

D. Wood, S. Eggers, and G. Gibson. SPUR memory system architecture. Technical Report UCB/CSD 87/394, Univ. of CA, Berkeley, Computer Science Division, Dec. 1987.

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