A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, "Verity - a formal verification program for custom CMOS circuits," IBM Journal of Research and Development, vol. 39, pp. 149--165, January/March 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....DELAYS TABLE IV ARRIVAL TIMES FOR THE nFET IN THE EXAMPLE CALCULATION OF (t ) APPENDIX II DETERMINING FET SIGNAL PROBABILITIES AND ARRIVAL TIME VALUES We first consider the calculation of the signal probabilities. If we let and denote two channel nodes of the CCC, then similar to [25], we can define the th path as one connection of FETs between and . We can also define a path function as a Boolean function indicating whether the th path is conducting. Let denote a controlling nFET gate input function in the path and let denote a controlling pFET gate input function in the ....

A. Kuehlmann, A. Srinivasan, and D. P. Lapotin, "Verity---A formal verification program for custom CMOS circuits," IBM J. Res. Develop., vol. 39, no. 1/2, pp. 149--165, 1995.

....be ascertained that the two views have the same functionality. Traditional verification techniques such as simulation or emulation do not provide a complete guarantee of correctness and can be very expensive in terms of necessary resources. Formal methods such as combinational equivalence checking [12] can be applied to complement traditional approaches and provide a proof of equivalence between two functional descriptions of a circuit. RTL and gate level models are both suitable functional representations and thus equivalence checking tools can operate directly on them. A switch level model, ....

....components (CCC) 2] A CCC comprises of a set of switches, a set of gates and a corresponding set of nets that are used to connect these components. The gate terminals of CCC switches and the input nets of CCC gates form the set of input nets that belong to a CCC (called controlling nets in [12]) According to basic laws of electronics, the logic values of all nets in a CCC can be determined from the logic values of the inputs of that CCC. The input nets of a CCC are further divided into two distinct sub sets. Internal CCC input nets are driven by the CCC itself and represent feedback ....

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Kuehlmann, A., Srinivasan, A., and LaPotin, D.P. Verity---a formal verification program for custom CMOS circuits. IBM Journal of Research and Development, vol. 39, no 1,2, January/March 1995.

....outdating the initial specifications. The design written in, say, synthesizable Verilog [32, 13] or VHDL [1, 31] is thus normally considered the reference model. Tools exist for efficiently checking equivalence between RTL descriptions and synthesized or manually generated netlist descriptions [16, 14]. In this environment, there are numerous possibilities for errors to be made that go undetected in the high level specification. Naturally, extensive testing is applied to remove these bugs. In fact, the cost of testing normally exceeds that of the original circuit design. However, with the ....

A. Kuehlmann, A. Srinivasan, and D. P. LaPotin. Verity--a formal verification program for custom CMOS circuits. IBM Journal of Research and Development, 39(1/2), January/March 1995. 18

.... several steps to execute an intruction, its ISA specification executes an instruction atomically in a single step, and the pipeline state can be related to the ISA state by an abstraction function that uses the pipeline flushing operation [12] Clock abstraction on dynamic switch level circuits [13, 14] generates gate level circuits without clocks to make their verification easier. Temporal abstraction hierarchies [15] have been used for efficient state space exploration. However, we are not aware of any compositional refinement checks between implementations and specifications that operate at ....

A. Kuehlmann, A. Srinivasan, and D. LaPotin, "Verity --- A formal verification program for custom CMOS circuits," IBM Journal on Research and Development, vol. 39, no. 12, pp. 149--165, 1995.

....of the loop snips (Assumption 8) The graph is then searched in a breadth first fashion to propagate noise through the network, and in the case of restoring segments, to perform the sensitivity tests required to ensure noise stability. In general, transistor path based functional extraction [20] guides three main types of sensitizations (Assumption 2) sensitization for coupled noise calculation on the output node of a CCC, sensitization for noise stability and propagated noise calculation from a given input, and sensitization for (a) b) Fig. 10. Noise graphs for the circuit of Fig. 9 ....

A. Kuehlmann, A. Srinivasan, and D. P. Lapotin, "Verity---A formal verification program for custom CMOS circuits," IBM J. Res. Dev., vol. 39, nos. 1/2, pp. 149--165, 1995.

....are known at the inputs of a CCC, these probabilities are translated into the FET signal probabilities and arrival time values for detailed body voltage estimation. We first consider the calculation of the signal probabilities. If we let i and j denote two channel nodes of the CCC, then similar to [15], we can define the kth path P k i;j as one connection of FETs between i and j. We can also define a path function f P k i;j as a Boolean function indicating whether the kth path is conducting. Let n i denote a controlling nFET gate input function in the path, and let p i denote a controlling ....

A. Kuehlmann, A. Srinivasan, and D. P. Lapotin. Verity -- a formal verification program for custom CMOS circuits. IBM Journal of Research and Development, 39(1/2):149 -- 165, 1995.

....systems and packet handlers for communication systems. It allows these designs to be verified at both an abstract level, and at the RTL level. From this level, designs may be either synthesized directly into logic gates, or compared to gate level designs using combination equivalence tools [KSL95] The methodology has in practice been applied to a very large design in a commercial design environment [Eir98] Nonetheless, there is no evidence to indicate that application of the methodology to additional designs will not reveal weaknesses which would require the incorporation of additional ....

A. Kuehlmann, A. Srinivasan, and D. P. LaPotin. Verity -- a formal verification program for custom CMOS circuits. IBM J. of Research and Development, 39(1--2):149--65, Jan.-- Mar. 1995.

....to work with the sampling operator. Working with specifications at an abstract level of temporal granularity is not new. Previous work on dynamic switch level circuits encountered similar situations, where it is useful to generate gate level circuits in which the clock is abstracted out [JBJ95, KSL95] previous work on reachability checking utilized the efficient exploration of temporal abstraction hierarchies [AHR98] However, we are not aware of any compositional refinement checks between implementations and specifications that operate at different time scales. In order to handle the proof ....

A. Kuehlmann, A. Srinivasan, and D.P. LaPotin. Verity - a formal verification program for custom CMOS circuits. IBM Journal on Research and Development, 39(1-2):149--165, 1995.

....could have detected the error in the Pentium, which was caused by a faulty quotient digit selection table. Later Rue , Shankar, and Srivas used SRI s general purpose theorem prover, PVS [Owre et al. 1992] on this same example [Rue et al. 1996] Processor designs. The Verity verification tool [Kuehlmann et al. 1995] is widely used within IBM in the design of many processors such as the PowerPC and System 390. Applied in a hierarchical manner, the tool can handle entire processor designs containing millions of transistors [Appenzeller and Kuehlmann 1995] Using this tool, the functional behavior of a hardware ....

....designs. The Verity verification tool [Kuehlmann et al. 1995] is widely used within IBM in the design of many processors such as the PowerPC and System 390. Applied in a hierarchical manner, the tool can handle entire processor designs containing millions of transistors [Appenzeller and Kuehlmann 1995]. Using this tool, the functional behavior of a hardware system at the register transfer level, gate level, or transistor level, is modeled as a boolean state transition function. Algorithms based on BDDs are used to check the equivalence of the state transition functions for different design ....

Kuehlmann, A., Srinivasan, A., and LaPotin, D. P. 1995. Verity - a formal verification program for custom CMOS circuits. IBM Journal of Research and Development 39, 1/2, 149--165.

....automatically and could have detected the error in the Pentium, which was caused by a faulty quotient digit selection table. Later Rue , Shankar, and Srivas used SRI s general purpose theorem prover, PVS [ORS92] on this same example [RSS96] ffl Processor designs. The Verity verification tool [KSL95] is widely used within IBM in the design of many processors such as the PowerPC and System 390. Applied in a hierarchical manner, the tool can handle entire processor designs containing millions of transistors [AK95] Using this tool, the functional behavior of a hardware system at the register ....

Andreas Kuehlmann, Arvind Srinivasan, and David P. LaPotin. Verity - a formal verification program for custom CMOS circuits. IBM Journal of Research and Development, 39(1/2):149-- 165, 1995.

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A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, "Verity - a formal verification program for custom CMOS circuits," IBM Journal of Research and Development, vol. 39, pp. 149--165, January/March 1995.

No context found.

A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, "Verity - a formal verification program for custom CMOS circuits," IBM Journal of Research and Development, vol. 39, pp. 149--165, January/March 1995.

....simulation performance and exposed to extensive simulation for confirming the compliance with the PowerPC architecture. The second view was a system implementation and was primarily custom designed on the transistor level to achieve optimal system performance. The verification program, Verity [3], was applied to exhaustively prove the functional equivalence of these two design representations. An industrial design environment necessitates the following challenges for formal verification, which need to be addressed in the chosen design methodology: ffl The verification approach must be ....

....statistics about the tool usage over the project duration. 2 Verity In this section we discuss those concepts of the verification tool Verity that are significant for the presented PowerPC verification methodology. A detailed description of the applied algorithms and methods can be found in [3]. Verity was designed for functional verification of large transistor and gate level circuits. It uses Reduced Ordered Binary Decision Diagrams (ROBDD) 4] for a canonical representation of logical functions and employes various heuristic ordering algorithms including dynamic variable ordering ....

A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, "Verity - a formal verification program for custom CMOS circuits," IBM Journal of Research and Development, vol. 39, pp. 149--166, January/March 1995.

No context found.

A. Kuehlmann et. al.: Verity - A Formal Verification Program for Custom CMOS Circuits. IBM Journal of Research and Development. Vol. 39, No.1/2.

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A. Kuehlmann, A. Srinivasan, D. P. LaPotin, "Verity---a formal verification program for custom CMOS circuits," IBM Journal of Research and Development, 39(1/2), January/March 1995.

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