A. B. Kahng, S. Muddu, E. Sarto, and R. Sharma, "Interconnect tuning strategies for high-performance ICs," in Proc. Conf. Design Automation Test Eur., 1998, pp. 471--478.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....In our model, we assume that buffers are constrained to be inserted for long enough wires such that the distance between adjacent buffers is lying within a range [low; up] given by the user. We call this the variable interval buffer insertion constraint [5, 1] For example, according to [7], global repeater rules for a high end microprocessor design in 0.25 m CMOS requires repeaters at intervals of at most 4500 m, and we can model this situation by assigning the low and up appropriately. In our floorplanner, we will divide a floorplan into a 2 dimensional grid structure and will ....

A. B. Kahng, S. Muddu, E. Sarto, and R. Sharma. Interconnect tuning strategies for high performance ics. In Pro. DATE, 1998.

....capacitance and mutual inductance, signals on neighboring wires may interfere with each other, causing excessive delay or loss of signal integrity. This effect, known as crosstalk, is more pronounced in deep submicron technology [8, 13] While many techniques have been proposed to reduce crosstalk [7, 10, 18], due to the limited design margin and unpredictable process variations, testing for crosstalk must be performed during manufacturing. In recent years, several crosstalk test generation techniques have been developed to generate tests for local interconnects in gate level circuits [5, 6, 9, 11, ....

A.B. Kahng, S. Muddu, E. Sarto, and R. Sharma, "Interconnect Tuning Strategies for High-Performance ICs," in Proceedings Design, Automation and Test in Europe, Paris, France, Feb. 1998, pp. 471--478.

....In our model, we assume that buffers are constrained to be inserted for long enough wires such that the distance between adjacent buffers is lying within a range [low; up] given by the user. We call this the variable interval buffer insertion constraint [5, 1] For example, according to [8], global repeater rules for a high end microprocessor design in the 0.25 m CMOS technology require repeaters at intervals of at most 4500 m, and we can model this situation by assigning the low and up appropriately. In our floorplanner, we will divide a floorplan into a 2 dimensional grid ....

....In addition, the wiring capacities are chosen such that unroutable wires will appear in our global routing test of those data sets. 15 No. of modules 33 49 62 (No. of nets, no. of two pin nets) 123, 265) 408, 504) 1611, 1946) g unit (m) 600 400 500 Wiring capacity 6 18 60 [low; up] 3,6] [4,8] [4,7] Table 1: Circuit Characteristics and Parameters Used in the Experiments Floorplanners F1 F2 F1 F2 F1 F2 Area (10 ) 129344.00 129661.00 39454.41 39754.35 99058.00 99254.00 Wirelength (10 m) 206.40 205.90 399.75 379.80 3067.60 2755.50 Congestion 2.27 2.21 0.13 0.12 25.60 ....

A. B. Kahng, S. Muddu, E. Sarto, and R. Sharma. Interconnect tuning strategies for high performance ics. In Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pages 471-- 478, 1998.

....for wire load[1] The increase of inter wire coupling capacitance makes crosstalk interference a serious problem for VLSI circuits[3, 7] Crosstalk causes logical malfunctions and delay faults. Especially for an on chip bus, crosstalk noise is a serious problem for modern and future VLSI design[8, 4]. Since each line of a bus runs in parallel for a long distance, the inter wire coupling capacitance between adjacent wires of the bus is relatively larger than other interconnects. Besides physical capacitance increase, simultaneous switching for opposite transition directions between adjacent ....

....VDEC chip fabrication service is used. The power supply voltage is 3.3V. The three types of bus line are simulated with capacitances C 0 , Cm , and resistance R as shown in table 1. Only Cm is changed because Cm is dominant for delay reduction. This capacitance and resistance are supposed from [4, 8], the bus length is 10mm. The number of repeaters which are inserted by regular interval for all lines is changed from 0 to 7. For each case of repeater insertion, #T is increased from 0ns to 5ns every 0.2ns step. T d is evaluated by measuring the time from 50 input transition of preceding ....

A.B. Kahng, S. Muddu, E. Sarto, and R. Sharma. Interconnect tuning strategies for high-performance ICs. Proc. of DATE98, pages 471--478, 1998.

....and mutual inductance, signals on neighboring wires may interfere with each other, causing excessive delay or loss of signal integrity. This effect, known as crosstalk, is more pronounced in deep submicron technology [2] 3] While many techniques have been proposed to reduce crosstalk [4][5], due to the limited design margin and unpredictable process variations, the testing of crosstalk must be addressed in manufacturing testing. Due to its timing nature, testing for crosstalk effect need to be conducted at the operational speed of the circuit under test. Atspeed testing for GHz ....

A.B. Kahng, S. Muddu, E. Sarto, and R. Sharma, "Interconnect tuning strategies for high-performance ICs," Proceedings Design, Automation and Test in Europe, Paris, France, Feb. 1998, pp.471-8.

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A. B. Kahng, S. Muddu, E. Sarto, and R. Sharma, "Interconnect tuning strategies for high-performance ICs," in Proc. Conf. Design Automation Test Eur., 1998, pp. 471--478.

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A. B. Kahng, S. Muddu, E. Sarto and R. Sharma, "Interconnect Tuning Strategies for High-Performance ICs", Proc. DATE, 1998.

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A.B. Kahng, S. Muddu, E. Sarto and R. Sharma, "Interconnect tuning strategies for high-performance ICs", Proc. DATE, 1998.

....with respect to feasible regions, and the buffer block plan implicitly contains the global buffering solution for the netlist of connections. However, in reality, multiple buffers are often needed per connection. For example, global repeater rules for a high end microprocessor design in 0. 25m CMOS [14] require repeater intervals of at most 4500m. 2 The number of buffers needed for a given connection depends strongly on the length of the connection; as noted in [14] the repeater interval is not only required for delay reduction, but also for crosstalk noise immunity and edge slewtime control. ....

....buffers are often needed per connection. For example, global repeater rules for a high end microprocessor design in 0.25m CMOS [14] require repeater intervals of at most 4500m. 2 The number of buffers needed for a given connection depends strongly on the length of the connection; as noted in [14], the repeater interval is not only required for delay reduction, but also for crosstalk noise immunity and edge slewtime control. We also note that buffer block resources may not always be completely plannable buffer sites are often embedded in IP blocks or in block collars within a ....

A. B. Kahng, S. Muddu, E. Sarto and R. Sharma, "Interconnect Tuning Strategies for High-Performance ICs", Proc. DATE, 1998.

....will make static timing results unreliable) and a peak noise limit of 15 of V dd is also typically desired. In Figure 5 we plot the delay uncertainty against wire width for four cases: SOI and bulk Si with and without the use of staggered repeaters. Staggered repeaters are introduced in [9] and exploit offset repeater placement on adjacent global lines to eliminate the impact of dynamic delay. In the bulk case there is no uncertainty (at least due to the two effects we consider) and in the SOI case all delay uncertainty is due to the floating body effect. As wire width increases, ....

A. B. Kahng, S. Muddu, E. Sarto and R. Sharma, "Interconnect Tuning Strategies for High-Performance ICs," Proc. DATE, 1998.

....connect process optimization must achieve more delicate balances, e.g. affording simultaneous distribution of signal, clock and power with adequate performance and reliability while minimizing die area. Also, more interconnect layers are required at each successive node in the technology roadmap [30, 8, 33], leading to a strong requirement for, e.g. planarized interconnect processes that rely on chemical mechanical polishing (CMP) Manufacturing steps involving CMP have varying effects on device and interconnect features, depending on local characteristics of the layout. This link between layout ....

A. B. KAHNG, S. MUDDU, E. SARTO, AND R. SHARMA, Interconnect Tuning Strategies for High-Performance ICs, in Proc. Conference on Design Automation and Test in Europe, February 1998.

....the design. Today s Rent like characterizations are based solely on topological structure; future models must capture delay and temporal structure 9 as well as communication and function complexity. Such new structural models will also facilitate such design activities as interconnect tuning [14]. ffl Prediction requires tool models as well. We need models of global optimization metaheuristics that allow prediction of output solution quality based on instance parameters and available CPU resource. Simple examples include (i) best so far curves for such iterative global optimizations as ....

A. B. Kahng, S. Muddu, E. Sarto and R. Sharma, "Interconnect Tuning Strategies for High-Performance ICs", Proc. Design, Automation and Test in Europe (DATE), Paris, February 1998.

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