T. Sakurai, A.R. Newton, "A simple MOSFET model for circuit analysis", IEEE Trans. Electron Devices, vol. 38, pp. 887-894, April 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....a closed form analytical expression characterizing the propagation delay of a CMOS inverter to be developed. In the following analysis, analytical expressions characterizing the transistor operating in the saturation region are extrapolated to approximate the time for the output signal to reach [37,38]. Therefore, based on this assumption, analytical expressions characterizing the propagation delay of each CMOS inverter within a two line and a three line coupled system are listed in Table 6. The e ect of the interconnect coupling capacitance on the propagation delay is characterized by and ....

T. Sakurai, A.R. Newton, A simple MOSFET model for circuit analysis, IEEE Trans. Electron Devices ED-38 (4) (1991) 887}894.

....estimating the propagation delay of a logic gate in a synchronous CMOS integrated circuit. A lumped model is applied in this paper to characterize the power supply rails in a synchronous CMOS integrated circuit. The submicrometer MOS transistors are modeled by the th power law I V model [14]. Analytical expressions are developed to characterize the on chip simultaneous noise and the output voltage waveform of a CMOS logic gate. The output voltage waveform based on the analytical expressions is quite close to SPICE. For a capacitive load, the maximum error of the propagation delay ....

....(14) 3 is the load capacitance. and are integration constants and can be determined from 4X U # and 4 4X U # . However, the effective output conductance of a MOS transistor also depends upon the output voltage in the linear region, changing from d 4X U to g d 4 U [14]. In order to accurately characterize the on chip simultaneous switching noise voltage, d is chosen between d 4X and g d 4X . 5 ; i can be expressed as 5 [ 5 t 2 F 2 F 3 d # ; i 2 3 d F D 2 3F 4X4 ....

[Article contains additional citation context not shown here]

T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, Vol. ED-38, No. 4, pp. 887--894, April 1991.

....registers and logic gates within a synchronous CMOS integrated circuit. The short channel MOS transistors are modeled as nonlinear devices and characterized by the th power law I V model, which is more accurate than the alpha power law model in both the linear region and the saturation region [13]. A CMOS logic gate in this discussion is modeled as a CMOS inverter. The power supply rail is characterized by a lumped model. The current through the PMOS transistor with a rising input signal, i.e. the short circuit current, is neglected in this discussion when determining the ....

T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, Vol. ED-38, No. 4, pp. 887--894, April 1991.

....should therefore be modeled as a lumped or distributed line. In order to evaluate the effects of on chip inductance on the behavior of a CMOS inverter, the interconnect is modeled here as a lumped , which is the load impedance of an interconnect line. The th power law model [6] is used to characterize the submicrometer MOS transistors. The th power law model is more accurate in the linear region and in determining the drain to source saturation voltage as compared to the alpha power law model [7] avoiding any discontinuity between the linear and saturation regions. ....

T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, Vol. ED-38, No. 4, pp. 887--894, April 1991.

....the same input slew rate. During a logic transition, only the active transistors are considered in the development of the analytical expressions. The MOS transistors are characterized by the ) LK power law model in the saturation region and the effective output resistance in the linear region [11]. 3 In Phase Transition The in phase transition is an optimistic condition in terms of the effect of the coupling capacitance on the propagation delay of a CMOS inverter. With an in phase transition, both inverters are assumed to transition in the same direction, for example, high to low at the ....

T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, Vol. ED-38, No. 4, pp. 887--894, April 1991.

....the gap between the classical Shichman Hodges model and more accurate, albeit complicated, I V models. However, this model is not sufficiently accurate in the linear region or to characterize the drain to source saturation voltage of a MOS transistor. An improved model, the th power law model [14], has also been proposed by Sakurai. The th power law model is used in this paper to derive tractable analytic equations to characterize the behavior of the circuit, thereby maintaining an intuitive unThis research was supported in part by the National Science Foundation under Grant No. ....

....waveform shape of the output voltage of a CMOS inverter as expressed in (8) is degraded with increasing interconnect resistance due to the . A : YX F term in (8) where the output voltage decreases due to the :C; term in the saturation region as compared to a capacitive load [7] [14]. Therefore, the interconnect resistance reduces the time during which a CMOS inverter remains in the saturation region. This effect is called resistive shielding [15] where a portion of the load capacitance is shielded in the saturation region when the load resistance is comparable to the ....

T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, Vol. ED-38, No. 4, pp. 887--894, April 1991.

....voltage down. However, in order to maintain performance, the threshold voltage should also be scaled down as well so that the gate drive, V gs V t ) remains large enough, since propagation delay in a CMOS gate can be approximated as: 2) where a is for modeling short channel effects [1] [2]. By reducing V dd , the switching power is reduced quadratically, but a reduction in V t causes an exponential increase in subthreshold leakage current. As one continues to scale down V dd and V t , the increased leakage power can dominate the dynamic switching power [3] In many event driven ....

T. Sakurai, R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, vol. 38, no. 4, pp. 887-894, April 1991.

....has the most significant impact on the power dissipation. This also avoids hot carrier effects in short channel devices. However, the threshold voltage V T has also to be scaled down because otherwise it has a much greater detrimental impact on the delay when small geometry devices are used [4]. Thus scaling V T by the same factor as V dd is needed so as not to adversely impact delay. However, reducing V T in small geometry MOSFETs results in a exponential increase in the stand by current [1] Simulation results given in [5] show that the power dissipation due to the standby current ....

....in most practical cases, the signal probabilities at the gate inputs and outputs are obtained by either local probability propagation or by logic simulation. 2.2 Delay Model 2.2. 1 Gate Delay Model An accurate and computationally efficient model for a short channel MOSFET is described in [4]. The model, called the nth power law, is an extension of the alphapower law model [3] but is much more accurate. The nth power law model has been shown to accurately represent the I Gamma V characteristics of short channel MOSFET s down to 0.25 m channel length. The CMOS inverter propagation ....

T. Sakurai and A. R. Newton "A Simple MOSFET Model for Circuit Analysis," IEEE Trans. on Eletron Devices, Vol. 38, No. 4, pp. 887-893, April 1991.

...., respectively. Voltages VO and VL are the voltages of CO and CL respectively. As for the drain current model of the MOSFETs, we use different models during and after input transition. In the analysis during input transition, we have adopted the n th power law model proposed by Sakurai and Newton [2]. It is expressed as follows. VDSAT = K(VGS 0 V TH ) m I DSAT = WE LE fi(V GS 0 V TH ) n I DS = I D5 = I DSAT (1 VDS ) V DS = VDSAT I DS = I D5 i 2 0 VDS VDSAT j VDS VDSAT :V DS VDSAT where K;m; n; fi are parameters of the n th power law model. This model is simple, but yet ....

T. Sakurai, and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. Electron Devices, vol. 38, no.4, pp. 887--893, Apr. 1991.

....CL . Finally, using logic level optimization techniques [6, 7] can reduce the switching activity E(t) in the circuit. Ideally, the threshold voltage V T should be scaled down by the same factor as V dd . This is due to the fact that delay is proportional to (1 Gamma V T =V dd ) Gamma1 . In [4] it is shown that not scaling V T down by the same factor as VDD has a greater (detrimental) impact on the delay when small geometry devices are used. The flipside of this is that reducing V T in small geometry MOSFETs results in an exponential increase in the stand by current [1] In fact, the ....

....may be computed exactly using BDDs. However, in most practical cases, the signal probabilities at the gate inputs and outputs are obtained by either local probability propagation or by logic simulation. An accurate and computationally efficient model for a short channel MOSFET is described in [4]. The model, called the nth power law, is an extension of the alpha power law model [3] and is more accurate. The nth power law model has been shown to accurately represent the I Gamma V characteristics of short channel MOSFET s down to a channel length of 0.25 m . The CMOS inverter ....

T. Sakurai and A. R. Newton "A Simple MOSFET Model for Circuit Analysis," IEEE Trans. on Electronic Devices, Vol. 38, No. 4, pp. 887-893, April 1991.

....waveform CGD = CGDO p CGDOn 1 2 CG p (1) ffl in the case of falling input CGD = CGDO p CGDOn 1 2 CGn (2) where subscripts n and p denote NMOS and PMOS, respectively. As for the drain current model of an MOSFET, we have adopted the n th power law model proposed by Sakurai and Newton [6]. It is expressed as follows. VDSAT = K(VGS 0 V TH ) m I DSAT = WE LE B(VGS 0 V TH ) n (3) i) VDS = VDSAT :saturation region I DS = I D5 = I DSAT (1 VDS ) 4) ii) VDS VDSAT :linear region I DS = I D5 2 0 VDS VDSAT VDS VDSAT (5) where K; m; n; B are parameters of the ....

T. Sakurai, and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. Electron Devices, vol. 38, no.4, pp. 887--893, Apr. 1991.

....is useful not only because its calculation speed is faster than circuit simulation but also it can be applied to various operating conditions once its parameters are characterized for that fabrication process. Much work has been done to analytically estimate the gate delay in static CMOS technology[2, 3, 4, 5, 6, 7, 8]. However these approaches assume a static capacitance as the output load of a gate, failed to provide an accurate estimation for the design of recent VLSI chips. Dartu et al. proposed an empirical gate delay model for gates driving a CRC load[9] This method pre characterizes an equivalent ....

....of a single MOSFET, which is common in that particular process technology. Parameters K;m; n; b1; b2; N1;N2;VTH2 should be determined for each block. We will examine how to calculate these parameters. Parameters VTH ; K;m; can be calculated in a way similar to the n th power law MOSFET model[3]. Parameter VTH2 represent the point where the drain current curve begins to be off from that represented by the n th power law MOSFET model for the low VGS region. We empirically set VTH2 to the middle point between the threshold voltage VTH and supply voltage VDD (VTH2 = VDD VTH ) 2) ....

T. Sakurai, and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. Electron Devices, vol. 38, no. 4, pp. 887-893, Apr. 1991.

....way unless we introduce some approximation. The major assumption we made is that the short circuit current can be approximated by a piece wise linear function of time. Considering all the current components under this assumption, and modeling MOSFET I V characteristics by Sakurai s n th power model[6], we have derived formulas for delay and power Table 2: Errors( in delay characterization Cell 0.8 m 0.5 m average maximum average maximum inv1 5.9 15.2 1.9 7.6 buf1 11.7 17.3 2.5 7.9 nand2 3.8 20.6 3.4 11.0 4.0 17.2 6.6 32.7 nand3 2.3 8.4 3.0 11.0 3.8 9.4 5.4 13.3 8.1 24.2 13.0 50.0 and2 ....

T. Sakurai and A.R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Trans. Dlectron Devices, Vol. 38, No. 4, pp. 887--893(1991).

....channel devices. However, the threshold voltage V T should also be scaled down since the delay is proportional to (1 Gamma V T =V dd ) Gamma1 . Furthermore, not scaling V T down by the same factor as VDD has a greater (detrimental) impact on the delay when small geometry devices are used [4]. The flipside of this is that reducing V T in small geometry MOSFETs results in an exponential increase in the standby current [1] Simulation results given in [5] show that the power dissipation due to the standby current dominates the switching power at very low threshold voltages. It is clear ....

....may be computed exactly using BDDs[6] However, in most practical cases, the signal probabilities at the gate inputs and outputs are obtained by either local probability propagation or by logic simulation. An accurate and computationally efficient model for a short channel MOSFET is described in [4]. The model, called the nth power law, is an extension of the alpha power law model [3] and is more accurate. The nth power law model has been shown to accurately represent the I Gamma V characteristics of short channel MOSFET s down to a channel length of 0.25 m . The CMOS inverter propagation ....

T. Sakurai and A. R. Newton "A Simple MOSFET Model for Circuit Analysis," IEEE Trans. on Electronic Devices, Vol. 38, No. 4, pp. 887-893, April 1991.

....as the transition time of the input signal, the amount of the capacitive load, the sizes of MOSFETs that make up the logic gate, etc. 1] which makes the analysis of CMOS logic gates non trivial. Several methods have been proposed for the analysis using different approximations. In reference [2] [3], simple closed formed formula of a propagation delay of a CMOS inverter circuit was derived. However the effect of short circuit current was neglected. Jeppson[4] and Embabi[5] derived delay formula Authors are with the Department of Communications and Computer Engineering, Kyoto University, ....

....by a piece wise linear function(Fig. 2) The error of the formula for a CMOS inverter is within 15 in many cases of our experiments. In this paper we present a formula for propagation delay considering a short circuit current using the n th power law MOSFET model proposed by Sakurai and Newton [3]. We show that the formula gives reasonable estimation compared with SPICE simulated delays. We discuss the accuracy of the delay formula for complex gates(e.g. NAND3) and the influence of short circuit current on propagation delay. II. Delay estimation We estimate propagation delay taking the ....

[Article contains additional citation context not shown here]

T. Sakurai, and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. Electron Devices, vol. 38, no.4, pp. 887--893, Apr. 1991.

No context found.

T. Sakurai, A.R. Newton, "A simple MOSFET model for circuit analysis", IEEE Trans. Electron Devices, vol. 38, pp. 887-894, April 1991.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC