G. S. Sohi, S. E. Breach, T. N. Vijaykumar. Multiscalar Processors. The 22 nd Annual International Symposium on Computer Architecture, pp. 414-425, June 1995. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
A Dynamic Multithreading Processor - Akkary, Driscoll (72 citations) (Correct)
....a simultaneous multithreading pipeline to increase processor utilization, except that the threads are created dynamically from the same program. Although the DMT processor is organized around dynamic simultaneous multiple threads, the execution model draws a lot from the multiscalar architecture [4,5]. The multiscalar implements mechanisms for multiple flows of control to avoid instruction fetch stalls and exploit control independence. It breaks up a program into tasks that execute concurrently on identical processing elements connected as a ring. Since the tasks are not independent, ....
G. S. Sohi, S. E. Breach, T. N. Vijaykumar. Multiscalar Processors. The 22 nd Annual International Symposium on Computer Architecture, pp. 414-425, June 1995.
Increasing Effective IPC by Exploiting Distant.. - Martel, Ortega.. (1999) (2 citations) (Correct)
.... to look for parallelism across basic block boundaries and support from effective branch prediction schemes [17, 28] This control speculation allows the simultaneous execution of instructions from different basic blocks and has originated some novel architectures like the ones in the multiscalar [18] and trace [16] processors. In order to further increase the number of instructions from which to exploit parallelism, multithreaded architectures [27, 23] have been proposed. Threads coming from the same application are usually found in parallel loops detected by the compiler [22] Hardware ....
G.S. Sohi, S.E. Breach, and T.N. Vijaykumar. Multiscalar processors. 22nd Annual International Symposium on Computer Architecture, June 1995.
Quantifying the Benefits of SPECint Distant.. - Ortega, Martel.. (Correct)
....is the enormous technological complexity they require. Detecting threads and recovering from misspeculation implies a lot of hardware that could be devoted to other computational tasks if threads could be statically explicited by the compiler. This reasoning is not new at all, the Multiscalar [18] architecture considered the exposure of threads as part of the compilers task. Compilers have successfully exploited thread level parallelism in regular control structures such as low level loops, as it is done by POLARIS [2] or SUIF [6] Even non structured parallelism can be automatically ....
G. Sohi, S. Breach, and T. Vijaykumar. Multiscalar processors. 22nd Annual International Symposium on Computer Architecture, June 1995.
Increasing Effective IPC by Exploiting Distant.. - Martel, Ortega.. (1999) (2 citations) (Correct)
.... for parallelism across basic block boundaries and support from effective branch prediction schemes [Smi81, YP92] This control speculation allows the simultaneous execution of instructions from different basic blocks and has originated some novel architectures like the ones in the multiscalar [SBV95] and trace [RJSS97] processors. In order to further increase the number of instructions from which to exploit parallelism, multithreaded architectures [YN95, TEE 95, TEL96] have been proposed. Threads coming from the same application are usually found in parallel loops detected by the ....
G.S. Sohi, S.E. Breach and T.N. Vijaykumar. Multiscalar processors. 22nd Annual International Symposium on Computer Architecture, 1995.
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